From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/width/SmallWidth.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/errors/width/SmallWidth.fir')

diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir
index 0ee60ec0..0885ba52 100644
--- a/test/errors/width/SmallWidth.fir
+++ b/test/errors/width/SmallWidth.fir
@@ -5,7 +5,7 @@ circuit Top :
   module Top : 
     output z : UInt
 
-    z := add(UInt<4>("h121"),UInt<3>("h13333"))
+    z <= add(UInt<4>("h121"),UInt<3>("h13333"))
 
 
 
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