From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/type/BulkConnect.fir | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'test/errors/type')

diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir
index 4e02402c..26f5c156 100644
--- a/test/errors/type/BulkConnect.fir
+++ b/test/errors/type/BulkConnect.fir
@@ -7,26 +7,26 @@ circuit Top :
   module Top : 
     wire a : { w : UInt<42>}
     wire b : { w : SInt<42>}
-    a <> b 
+    a <- b 
 
     wire c : { w : UInt<10>}
     wire d : { flip w : UInt<12> }
-    c <> d
+    c <- d
 
     wire e : { w : UInt<10>}
     wire f : { x : UInt<12> }
-    e <> f
+    e <- f
 
     wire g : { w : { y : UInt<10> }}
     wire h : { w : { x : UInt<12> }}
-    g <> h
+    g <- h
 
     wire i : { w : { flip y : UInt<10> }}
     wire j : { w : { y : UInt<12> }}
-    i <> j
+    i <- j
 
     wire k : { w : { y : SInt<10> }}
     wire l : { w : { y : UInt<12> }}
-    k <> l
+    k <- l
 
 
-- 
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