From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/init/Output.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/errors/init')

diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir
index f28d1e0b..0b7a7f80 100644
--- a/test/errors/init/Output.fir
+++ b/test/errors/init/Output.fir
@@ -7,4 +7,4 @@ circuit Top :
     wire y : UInt<1>
 
     when UInt(0) : 
-      y := UInt(1)
+      y <= UInt(1)
-- 
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