From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/high-form/NegUInt.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/errors/high-form/NegUInt.fir')

diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir
index 35f25013..8249f791 100644
--- a/test/errors/high-form/NegUInt.fir
+++ b/test/errors/high-form/NegUInt.fir
@@ -4,4 +4,4 @@
 circuit Top :
   module Top :
     wire x : UInt<4>
-    x := UInt(-2)
+    x <= UInt(-2)
-- 
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