From 5d3061bfed8445370e6fa97ec9238ba49e8fafbc Mon Sep 17 00:00:00 2001 From: azidar Date: Mon, 24 Aug 2015 11:45:37 -0700 Subject: Changed all tests to use verilog backend. --- test/errors/high-form/InstanceNotModule.fir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test/errors/high-form/InstanceNotModule.fir') diff --git a/test/errors/high-form/InstanceNotModule.fir b/test/errors/high-form/InstanceNotModule.fir index 7c4d152a..aa49b26b 100644 --- a/test/errors/high-form/InstanceNotModule.fir +++ b/test/errors/high-form/InstanceNotModule.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ; CHECK: Module Top2 is not defined. circuit Top : -- cgit v1.2.3