From 5694a8808bd724b820caca2f5f1176b8c1e3f40d Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 20 Aug 2015 15:35:43 -0700
Subject: Added tests, cleaned up repo

---
 test/errors/gender/ReadOutput.fir | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 test/errors/gender/ReadOutput.fir

(limited to 'test/errors/gender')

diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir
new file mode 100644
index 00000000..14ac75c1
--- /dev/null
+++ b/test/errors/gender/ReadOutput.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Expression out$y is used as a sink but can only be used as a source.
+
+circuit BTB :
+  module BTB : 
+    output out : {x : UInt<1>, flip y : UInt<1>}
+
+    wire w : {x : UInt<1>, flip y : UInt<1>}
+    w.x := UInt(1)
+    w.y := UInt(1)
+    out.x := UInt(1)
+    w <> out
-- 
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