From cf80ff9c83c2fedd42ec186a3e342520c89f91ab Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 May 2015 17:33:40 -0700
Subject: Added <>. Added additional checks for primops. Added new chisel3
 files.

---
 test/chisel3/Rom.fir | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 test/chisel3/Rom.fir

(limited to 'test/chisel3/Rom.fir')

diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir
new file mode 100644
index 00000000..8e80b7d4
--- /dev/null
+++ b/test/chisel3/Rom.fir
@@ -0,0 +1,27 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit Rom : 
+  module Rom : 
+    output out : UInt<5>
+    input addr : UInt<4>
+    
+    wire r : UInt<5>[16]
+    r[0] := UInt<5>(0)
+    r[1] := UInt<5>(2)
+    r[2] := UInt<5>(4)
+    r[3] := UInt<5>(6)
+    r[4] := UInt<5>(8)
+    r[5] := UInt<5>(10)
+    r[6] := UInt<5>(12)
+    r[7] := UInt<5>(14)
+    r[8] := UInt<5>(16)
+    r[9] := UInt<5>(18)
+    r[10] := UInt<5>(20)
+    r[11] := UInt<5>(22)
+    r[12] := UInt<5>(24)
+    r[13] := UInt<5>(26)
+    r[14] := UInt<5>(28)
+    r[15] := UInt<5>(30)
+    accessor T_39 = r[addr]
+    out := T_39
-- 
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