From df4bae5c7a95d3a56f95d86212f083b7ba121da7 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 7 Jul 2015 10:13:29 -0700
Subject: Pass most tests. The ones that do not pass are not expected to, yet

---
 test/chisel3/Risc.fir | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'test/chisel3/Risc.fir')

diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir
index 425f8a91..a1ba01b9 100644
--- a/test/chisel3/Risc.fir
+++ b/test/chisel3/Risc.fir
@@ -14,23 +14,23 @@ circuit Risc :
     cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
-    accessor inst = code[pc]
+    infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_51 = eq(rai, UInt<1>(0))
-    accessor T_52 = file[rai]
+    infer accessor T_52 = file[rai]
     node ra = mux(T_51, UInt<1>(0), T_52)
     node T_53 = eq(rbi, UInt<1>(0))
-    accessor T_54 = file[rbi]
+    infer accessor T_54 = file[rbi]
     node rb = mux(T_53, UInt<1>(0), T_54)
     wire rc : UInt<32>
     valid := UInt<1>(0)
     out := UInt<1>(0)
     rc := UInt<1>(0)
     when isWr : 
-      accessor T_55 = code[wrAddr]
+      infer accessor T_55 = code[wrAddr]
       T_55 := wrData
     else : when boot : pc := UInt<1>(0)
       else : 
@@ -47,7 +47,7 @@ circuit Risc :
         node T_61 = eq(rci, UInt<8>(255))
         when T_61 : valid := UInt<1>(1)
         else : 
-          accessor T_62 = file[rci]
+          infer accessor T_62 = file[rci]
           T_62 := rc
         node T_63 = add-wrap(pc, UInt<1>(1))
         pc := T_63
-- 
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