From 723c48b1ed0c341a10d1eba5a226787c33398505 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 1 May 2015 13:44:53 -0700
Subject: Fixed performance bug where PlusWidth, MinusWidth, and ExpWidth could
 be simplified earlier, and also now have equal? defined so mMaxWidth doesn't
 blow up during width inference

---
 test/chisel3/Mul.fir | 61 +++++++++++++++++++++-------------------------------
 1 file changed, 24 insertions(+), 37 deletions(-)

(limited to 'test/chisel3/Mul.fir')

diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index 1ce6f797..ec991197 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -1,45 +1,32 @@
 ; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
 ; CHECK: Done!
+
 circuit Mul : 
   module Mul : 
-    input y : UInt<2>
     input x : UInt<2>
     output z : UInt<4>
+    output a : UInt<4>
+    input y : UInt<2>
     
-    node T_43 = UInt<4>(0)
-    node T_44 = UInt<4>(0)
-    node T_45 = UInt<4>(0)
-    node T_46 = UInt<4>(0)
-    node T_47 = UInt<4>(0)
-    node T_48 = UInt<4>(1)
-    node T_49 = UInt<4>(2)
-    node T_50 = UInt<4>(3)
-    node T_51 = UInt<4>(0)
-    node T_52 = UInt<4>(2)
-    node T_53 = UInt<4>(4)
-    node T_54 = UInt<4>(6)
-    node T_55 = UInt<4>(0)
-    node T_56 = UInt<4>(3)
-    node T_57 = UInt<4>(6)
-    node T_58 = UInt<4>(9)
     wire tbl : UInt<4>[16]
-    tbl[0] := T_43
-    tbl[1] := T_44
-    tbl[2] := T_45
-    tbl[3] := T_46
-    tbl[4] := T_47
-    tbl[5] := T_48
-    tbl[6] := T_49
-    tbl[7] := T_50
-    tbl[8] := T_51
-    tbl[9] := T_52
-    tbl[10] := T_53
-    tbl[11] := T_54
-    tbl[12] := T_55
-    tbl[13] := T_56
-    tbl[14] := T_57
-    tbl[15] := T_58
-    node T_60 = shl(x, 2)
-    node T_61 = bit-or(T_60, y)
-    accessor T_62 = tbl[T_61]
-    z := T_62
+    tbl[0] := UInt<4>(0)
+    tbl[1] := UInt<4>(0)
+    tbl[2] := UInt<4>(0)
+    tbl[3] := UInt<4>(0)
+    tbl[4] := UInt<4>(0)
+    tbl[5] := UInt<4>(1)
+    tbl[6] := UInt<4>(2)
+    tbl[7] := UInt<4>(3)
+    tbl[8] := UInt<4>(0)
+    tbl[9] := UInt<4>(2)
+    tbl[10] := UInt<4>(4)
+    tbl[11] := UInt<4>(6)
+    tbl[12] := UInt<4>(0)
+    tbl[13] := UInt<4>(3)
+    tbl[14] := UInt<4>(6)
+    tbl[15] := UInt<4>(9)
+    node T_43 = shl(x, 2)
+    node ad = bit-or(Pad(T_43,?), Pad(y,?))
+    a := Pad(ad,?)
+    accessor T_44 = tbl[ad]
+    z := Pad(T_44,?)
-- 
cgit v1.2.3


From 93ba0196dc2ba88e4e34346e5fbc105743a8eaa0 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 2 May 2015 12:20:41 -0700
Subject: Now when expanding ConnectFrom/ToIndex, create a node for the index
 so it isn't duplicated for all the whens

---
 test/chisel3/Mul.fir | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

(limited to 'test/chisel3/Mul.fir')

diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index ec991197..46a8c9b9 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -1,12 +1,10 @@
 ; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
 ; CHECK: Done!
-
 circuit Mul : 
   module Mul : 
     input x : UInt<2>
-    output z : UInt<4>
-    output a : UInt<4>
     input y : UInt<2>
+    output z : UInt<4>
     
     wire tbl : UInt<4>[16]
     tbl[0] := UInt<4>(0)
@@ -25,8 +23,7 @@ circuit Mul :
     tbl[13] := UInt<4>(3)
     tbl[14] := UInt<4>(6)
     tbl[15] := UInt<4>(9)
-    node T_43 = shl(x, 2)
-    node ad = bit-or(Pad(T_43,?), Pad(y,?))
-    a := Pad(ad,?)
-    accessor T_44 = tbl[ad]
+    node T_42 = shl(x, 2)
+    node T_43 = bit-or(Pad(T_42,?), Pad(y,?))
+    accessor T_44 = tbl[T_43]
     z := Pad(T_44,?)
-- 
cgit v1.2.3