From f8f9de58dbba5e53193246a5fd2145dfe6537e10 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 10:41:27 -0700
Subject: Added sequential/combinational memories. Started debugging verilog
 backend. Added Long support so UInt(LARGENUMBER) works

---
 test/chisel3/ModuleWire.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/chisel3/ModuleWire.fir')

diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir
index fefe42bd..3be7f928 100644
--- a/test/chisel3/ModuleWire.fir
+++ b/test/chisel3/ModuleWire.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit ModuleWire : 
-- 
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