From 3b3e1117fa3f346e70d3b8d50b7fd91842fb753b Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 22 Apr 2015 10:07:58 -0700
Subject: Added new test that breaks current parser. updated todo

---
 test/chisel3/ModuleVec.fir | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 test/chisel3/ModuleVec.fir

(limited to 'test/chisel3/ModuleVec.fir')

diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
new file mode 100644
index 00000000..7198667a
--- /dev/null
+++ b/test/chisel3/ModuleVec.fir
@@ -0,0 +1,30 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit ModuleVec : 
+  module PlusOne : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_33 = UInt(1, 1)
+    node T_34 = add(in, T_33)
+    out := T_34
+  module PlusOne_25 : 
+    input in : UInt(32)
+    output out : UInt(32)
+    
+    node T_35 = UInt(1, 1)
+    node T_36 = add(in, T_35)
+    out := T_36
+  module ModuleVec : 
+    output ins : UInt(32)[2]
+    output outs : UInt(32)[2]
+    
+    inst T_37 of PlusOne
+    inst T_38 of PlusOne_25
+    wire pluses : {flip in : UInt(32), out : UInt(32)}[2]
+    pluses.0 := T_37
+    pluses.1 := T_38
+    pluses.s.in := ins.s
+    outs.0 := pluses.s.out
+    pluses.s.in := ins.1
+    outs.1 := pluses.1.out
-- 
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