From 7992c5f7725bcbf00c1130c50719711b19dc9818 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 29 Apr 2015 15:41:57 -0700
Subject: Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct

---
 test/chisel3/ModuleVec.fir | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'test/chisel3/ModuleVec.fir')

diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7379024b..a4617267 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -6,25 +6,25 @@ circuit ModuleVec :
     output out : UInt<32>
     
     node T_33 = UInt<1>(1)
-    node T_34 = add(in, T_33)
-    out := T_34
+    node T_34 = add-wrap(Pad(in,?), Pad(T_33,?))
+    out := Pad(T_34,?)
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
     node T_35 = UInt<1>(1)
-    node T_36 = add(in, T_35)
-    out := T_36
+    node T_36 = add-wrap(Pad(in,?), Pad(T_35,?))
+    out := Pad(T_36,?)
   module ModuleVec : 
-    output ins : UInt<32>[2]
+    input ins : UInt<32>[2]
     output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
-    pluses[0] := T_37
-    pluses[1] := T_38
-    pluses.s.in := ins.s
-    outs[0] := pluses.s.out
-    pluses.s.in := ins[1]
-    outs[1] := pluses[1].out
+    wire pluses : { in : UInt<32>, flip out : UInt<32>}[2]
+    pluses[0] := Pad(T_37,?)
+    pluses[1] := Pad(T_38,?)
+    pluses[0].in := Pad(ins[0],?)
+    outs[0] := Pad(pluses[0].out,?)
+    pluses[1].in := Pad(ins[1],?)
+    outs[1] := Pad(pluses[1].out,?)
-- 
cgit v1.2.3