From 887d785ecc2ba7c363194cef89b72bc026c81cf9 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 3 Jun 2015 20:39:41 -0700
Subject: Fixed verilog backend bugs. Passes ALU. Fails Datapath

---
 test/chisel3/Datapath.fir | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'test/chisel3/Datapath.fir')

diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index 10643549..c02eeae6 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -195,12 +195,12 @@ circuit Datapath :
     when T_555 : 
       node T_556 = eq(addr, UInt<12>(1310))
       when T_556 : 
-        node T_557 = dshl(UInt<1>(1), src)
+        node T_557 = dshl(UInt<1>(1), bits(src,5,0))
         node T_558 = bit-or(data, T_557)
         reg_tohost := T_558
       node T_559 = eq(addr, UInt<12>(1290))
       when T_559 : 
-        node T_560 = dshl(UInt<1>(1), src)
+        node T_560 = dshl(UInt<1>(1), bits(src,5,0))
         node T_561 = bit-or(data, T_560)
         reg_status := T_561
     node T_562 = eq(cmd, UInt<2>(3))
@@ -209,12 +209,12 @@ circuit Datapath :
     when T_564 : 
       node T_565 = eq(addr, UInt<12>(1310))
       when T_565 : 
-        node T_566 = dshl(UInt<1>(0), src)
+        node T_566 = dshl(UInt<1>(0), bits(src,5,0))
         node T_567 = bit-and(data, T_566)
         reg_tohost := T_567
       node T_568 = eq(addr, UInt<12>(1290))
       when T_568 : 
-        node T_569 = dshl(UInt<1>(0), src)
+        node T_569 = dshl(UInt<1>(0), bits(src,5,0))
         node T_570 = bit-and(data, T_569)
         reg_status := T_570
   module Datapath : 
-- 
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