From 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 24 Aug 2015 10:58:49 -0700
Subject: Removed old chisel3 tests that all failed for syntax reasons. Tests
 should now be small examples, categorized by either passes, errors, or
 features.

---
 test/chisel3/Counter.fir | 17 -----------------
 1 file changed, 17 deletions(-)
 delete mode 100644 test/chisel3/Counter.fir

(limited to 'test/chisel3/Counter.fir')

diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
deleted file mode 100644
index 0f80f687..00000000
--- a/test/chisel3/Counter.fir
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit Counter : 
-  module Counter : 
-    input inc : UInt<1>
-    output tot : UInt<8>
-    input amt : UInt<4>
-    
-    reg T_13 : UInt<8>
-    on-reset T_13 := UInt<8>(0)
-    when inc : 
-      node T_14 = add-wrap(T_13, amt)
-      node T_15 = gt(T_14, UInt<8>(255))
-      node T_16 = mux(T_15, UInt<1>(0), T_14)
-      T_13 := T_16
-    tot := T_13
-- 
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