From 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 16 Apr 2015 17:05:46 -0700
Subject: Updated parser to correctly read empty statements

---
 test/chisel3/Counter.fir | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

(limited to 'test/chisel3/Counter.fir')

diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
index 8bab249c..55091d7f 100644
--- a/test/chisel3/Counter.fir
+++ b/test/chisel3/Counter.fir
@@ -1,17 +1,20 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit Counter : 
   module Counter : 
     input inc : UInt(1)
     output tot : UInt(8)
     input amt : UInt(4)
     
-    node T_13 : UInt(8) = UInt(255, 8)
-    node T_14 : UInt(8) = UInt(0, 8)
+    node T_13 = UInt(255, 8)
+    node T_14 = UInt(0, 8)
     reg T_15 : UInt(8)
     T_15.init := T_14
     when inc : 
-      node T_16 : UInt = add-mod(T_15, amt)
-      node T_17 : UInt(1) = greater(T_16, T_13)
-      node T_18 : UInt(1) = UInt(0, 1)
-      node T_19 : UInt(1) = multiplex(T_17, T_18, T_16)
+      node T_16 = add-wrap(T_15, amt)
+      node T_17 = gt(T_16, T_13)
+      node T_18 = UInt(0, 1)
+      node T_19 = mux(T_17, T_18, T_16)
       T_15 := T_19
-    tot := T_15
\ No newline at end of file
+    tot := T_15
+;CHECK: Finished To Flo
-- 
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