From f8f9de58dbba5e53193246a5fd2145dfe6537e10 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 2 Jun 2015 10:41:27 -0700
Subject: Added sequential/combinational memories. Started debugging verilog
 backend. Added Long support so UInt(LARGENUMBER) works

---
 test/chisel3/Core.fir | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'test/chisel3/Core.fir')

diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index b81eb7e9..06010573 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
 
 circuit Core : 
@@ -97,7 +97,7 @@ circuit Core :
     input waddr : UInt<5>
     input wdata : UInt<32>
     
-    mem regs : UInt<32>[32]
+    cmem regs : UInt<32>[32]
     node T_1286 = eq(raddr1, UInt<1>(0))
     node T_1287 = bit-not(T_1286)
     accessor T_1288 = regs[raddr1]
-- 
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