From f3af49a75c2969484e07447223c7cde6852a0119 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 15 Jan 2016 15:45:41 -0800 Subject: Extraction inputs are no longer cast --- src/main/stanza/verilog.stanza | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index 0e1c97c3..9bbb9aae 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -152,8 +152,8 @@ defn emit (e:Expression) -> String : BIT-OR-OP : [emit-as-type(args(e)[0],type(e)) " | " emit-as-type(args(e)[1],type(e))] BIT-XOR-OP : [emit-as-type(args(e)[0],type(e)) " ^ " emit-as-type(args(e)[1],type(e))] CONCAT-OP : ["{" emit-as-type(args(e)[0],type(e)) "," emit-as-type(args(e)[1],type(e)) "}"] - BIT-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] "]"] - BITS-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] ":" consts(e)[1] "]"] + BIT-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] "]"] + BITS-SELECT-OP : [emit(args(e)[0]) "[" consts(e)[0] ":" consts(e)[1] "]"] BIT-AND-REDUCE-OP : var v = emit-as-type(args(e)[0],type(e)) for x in tail(args(e)) do : -- cgit v1.2.3