From f1533a5030e8d04a1cb2fa333f5224abfdac9915 Mon Sep 17 00:00:00 2001
From: Jack
Date: Tue, 15 Mar 2016 16:49:33 -0700
Subject: Change non-reentrant VerilogEmitter from object to class

---
 src/main/scala/firrtl/Compiler.scala | 3 ++-
 src/main/scala/firrtl/Emitter.scala  | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index aa3eeace..c0fa78f0 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -91,7 +91,8 @@ object VerilogCompiler extends Compiler {
   def run(c: Circuit, w: Writer)
   {
     val loweredIR = PassUtils.executePasses(c, passes)
-    VerilogEmitter.run(loweredIR, w)
+    val verilogEmitter = new VerilogEmitter
+    verilogEmitter.run(loweredIR, w)
   }
 
 }
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 2aee699d..79b1847d 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -54,7 +54,7 @@ object FIRRTLEmitter extends Emitter {
 
 case class VIndent()
 case class VRandom()
-object VerilogEmitter extends Emitter {
+class VerilogEmitter extends Emitter {
    val tab = "   "
    val ran = VRandom()
    var w:Option[Writer] = None
-- 
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