From ec82fa81c98cbffea673169b02c85b5b1375e0ef Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 27 Apr 2020 15:20:10 -0700
Subject: Fix remaining 'removed in 1.3' deprecations (#1542)

* Bump old 'removed in 1.3' deprecation
* Remove outdated passes.VerilogRename
* Fixes #1467---
 src/main/scala/firrtl/LoweringCompilers.scala    |  2 +-
 src/main/scala/firrtl/passes/VerilogRename.scala | 11 -----------
 2 files changed, 1 insertion(+), 12 deletions(-)
 delete mode 100644 src/main/scala/firrtl/passes/VerilogRename.scala

(limited to 'src')

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index d29ab367..14d222f6 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -6,7 +6,7 @@ import firrtl.transforms.IdentityTransform
 import firrtl.options.StageUtils
 import firrtl.stage.{Forms, TransformManager}
 
-@deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.3.", "1.2")
+@deprecated("Use a TransformManager or some other Stage/Phase class. Will be removed in 1.4.", "FIRRTL 1.2")
 sealed abstract class CoreTransform extends SeqTransform
 
 /** This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting
diff --git a/src/main/scala/firrtl/passes/VerilogRename.scala b/src/main/scala/firrtl/passes/VerilogRename.scala
deleted file mode 100644
index 4d51128c..00000000
--- a/src/main/scala/firrtl/passes/VerilogRename.scala
+++ /dev/null
@@ -1,11 +0,0 @@
-package firrtl.passes
-import firrtl.ir.Circuit
-import firrtl.transforms.VerilogRename
-
-@deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
-object VerilogRename extends Pass {
-  override def run(c: Circuit): Circuit = new VerilogRename().run(c)
-  @deprecated("Use transforms.VerilogRename, will be removed in 1.3", "1.2")
-  def verilogRenameN(n: String): String =
-    if (firrtl.Utils.v_keywords(n)) "%s$".format(n) else n
-}
-- 
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