From ec32c852b57a42c7741f8ae27d59c21fcdb86a82 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 21 Apr 2016 14:29:44 -0700
Subject: Avoid Lint errors connecting wide signals to narrow ones

---
 src/main/scala/firrtl/Compiler.scala      |  2 +-
 src/main/scala/firrtl/passes/Passes.scala | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 69450a67..fda4b7e3 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -73,11 +73,11 @@ object VerilogCompiler extends Compiler {
     RemoveAccesses,
     ExpandWhens,
     CheckInitialization,   
-    Legalize,
     ResolveKinds,
     InferTypes,
     ResolveGenders,
     InferWidths,
+    Legalize,
     LowerTypes,
     ResolveKinds,
     InferTypes,
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index f7526897..bfe2a3cc 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -1159,6 +1159,18 @@ object Legalize extends Pass {
     }
     case _ => e
   }
+  def legalizeConnect(c: Connect): Stmt = {
+    val t = tpe(c.loc)
+    val w = long_BANG(t)
+    if (w >= long_BANG(tpe(c.exp))) c
+    else {
+      val newType = t match {
+        case _: UIntType => UIntType(IntWidth(w))
+        case _: SIntType => SIntType(IntWidth(w))
+      }
+      Connect(c.info, c.loc, DoPrim(BITS_SELECT_OP, Seq(c.exp), Seq(w-1, 0), newType))
+    }
+  }
   def run (c: Circuit): Circuit = {
     def legalizeE (e: Expression): Expression = {
       e map (legalizeE) match {
@@ -1166,7 +1178,13 @@ object Legalize extends Pass {
         case e => e
       }
     }
-    def legalizeS (s: Stmt): Stmt = s map (legalizeS) map (legalizeE)
+    def legalizeS (s: Stmt): Stmt = {
+      val legalizedStmt = s match {
+        case c: Connect => legalizeConnect(c)
+        case _ => s
+      }
+      legalizedStmt map legalizeS map legalizeE
+    }
     def legalizeM (m: Module): Module = m map (legalizeS)
     Circuit(c.info, c.modules.map(legalizeM), c.main)
   }
-- 
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