From e4e6c8cb3e8876aa468497917ecff7ebfff567a4 Mon Sep 17 00:00:00 2001
From: jackbackrack
Date: Tue, 2 Jun 2015 08:48:46 -0700
Subject: turn off eliminate-temps until improved

---
 src/main/stanza/compilers.stanza | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 0c3978ab..67c6bfeb 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -41,13 +41,8 @@ public defstruct StandardVerilog <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardVerilog) -> List<Pass> :
    to-list $ [
-<<<<<<< HEAD
-      CheckHighForm()
-      ;; TempElimination()
-=======
       CheckHighForm(expand-delin)
-      TempElimination()
->>>>>>> upstream/master
+      ;; TempElimination()
       ToWorkingIR()
       MakeExplicitReset()
       ResolveKinds()
-- 
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