From dbee203d680d3b74c78da35528df721acc6bb22e Mon Sep 17 00:00:00 2001
From: chick
Date: Fri, 23 Sep 2016 16:05:13 -0700
Subject: Use empty-parens as appropriate for f: => Unit calls

---
 src/main/scala/firrtl/Emitter.scala                    | 4 ++--
 src/main/scala/firrtl/passes/CheckChirrtl.scala        | 2 +-
 src/main/scala/firrtl/passes/CheckInitialization.scala | 2 +-
 src/main/scala/firrtl/passes/Checks.scala              | 8 ++++----
 src/main/scala/firrtl/passes/ReplaceMemMacros.scala    | 2 +-
 5 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 435bc484..d699064c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -640,9 +640,9 @@ class VerilogEmitter extends Emitter {
       }
 
       build_netlist(m.body)
-      build_ports
+      build_ports()
       build_streams(m.body)
-      emit_streams
+      emit_streams()
       m
    }
 
diff --git a/src/main/scala/firrtl/passes/CheckChirrtl.scala b/src/main/scala/firrtl/passes/CheckChirrtl.scala
index 771577be..21628633 100644
--- a/src/main/scala/firrtl/passes/CheckChirrtl.scala
+++ b/src/main/scala/firrtl/passes/CheckChirrtl.scala
@@ -149,7 +149,7 @@ object CheckChirrtl extends Pass {
       case 1 =>
       case _ => errors append new NoTopModuleException(c.info, c.main)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 7d7f2f32..12b83c55 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -116,7 +116,7 @@ object CheckInitialization extends Pass {
       case m: Module => checkInitM(m)
       case m => // Do nothing
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index d5fbdeeb..082544c0 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -222,7 +222,7 @@ object CheckHighForm extends Pass {
       case 1 =>
       case _ => errors append new NoTopModuleException(c.info, c.main)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -419,7 +419,7 @@ object CheckTypes extends Pass {
     }
 
     c.modules foreach (m => m map check_types_s(m.info, m.name))
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -522,7 +522,7 @@ object CheckGenders extends Pass {
       genders ++= (m.ports map (p => p.name -> to_gender(p.direction)))
       m map check_genders_s(m.info, m.name, genders)
     }
-    errors.trigger
+    errors.trigger()
     c
   }
 }
@@ -594,7 +594,7 @@ object CheckWidths extends Pass {
     }
 
     c.modules foreach check_width_m
-    errors.trigger
+    errors.trigger()
     c
   }
 }
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index 33a371a0..2e6ba3cc 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -118,7 +118,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
     val memMods = new Modules
     val modules = c.modules map updateMemMods(namespace, memMods)
     // print conf
-    writer.serialize
+    writer.serialize()
     c copy (modules = modules ++ memMods)
   }  
 }
-- 
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