From d836fed6968d78210bd926cd14f9d26f150fc82d Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Fri, 4 Sep 2020 09:15:50 -0700
Subject: Legalize memory port clocks

---
 src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala b/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala
index 5a1ccdbf..0edf0cc6 100644
--- a/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala
+++ b/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala
@@ -52,6 +52,9 @@ object LegalizeClocksAndAsyncResetsTransform {
           (None, rxClock)
         }
         Block(clockNodeOpt ++: resetNodeOpt ++: Seq(rx))
+      case Connect(info, loc, rhs @ DoPrim(_, _, _, ClockType)) if (Utils.kind(loc) == MemKind) =>
+        val node = DefNode(info, namespace.newTemp, rhs)
+        Block(node, Connect(info, loc, WRef(node)))
       case p: Print if isLiteralExpression(p.clk) =>
         val node = DefNode(p.info, namespace.newTemp, p.clk)
         val px = p.copy(clk = WRef(node))
-- 
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