From 5298af3dffcd0985922a2a8317fa6a67e192a9c0 Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Sat, 18 Apr 2015 13:23:16 -0700 Subject: change to have flo file go to a file --- src/main/stanza/firrtl-main.stanza | 10 ++++++++-- src/main/stanza/firrtl-test-main.stanza | 11 ++++++++--- src/main/stanza/passes.stanza | 17 ++++++++--------- 3 files changed, 24 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza index 92bb066f..fe9b49fa 100644 --- a/src/main/stanza/firrtl-main.stanza +++ b/src/main/stanza/firrtl-main.stanza @@ -21,10 +21,16 @@ defpackage firrtl-main : defn main () : val arg = commandline-arguments() val args = split(arg,' ') - val lexed = lex-file(args[1]) + val pathname = args[1] + val lexed = lex-file(pathname) val c = parse-firrtl(lexed) ;println(c) - run-passes(c,to-list(args[2])) + val dir = "." ;; could have dir arg + val name = last(split(pathname,'/')) + val basename = split(name,'.')[0] + val outname = string-join([dir "/" basename ".flo"]) + val c* = run-passes(c, to-list(args[2]), outname) + ;; run-passes(c,to-list(args[2])) main() diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 991f7cf6..ca521ec2 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -28,14 +28,19 @@ defn set-printvars! (p:List) : defn main () : val args = commandline-arguments() - val lexed = lex-file(args[1]) + val pathname = args[1] + val lexed = lex-file(pathname) val c = parse-firrtl(lexed) + val dir = "." ;; could have dir arg + val name = last(split(pathname,'/')) + val basename = split(name,'.')[0] + val outname = string-join([dir "/" basename ".flo"]) if length(args) >= 4 : set-printvars!(to-list(args[3])) if length(args) >= 3 : - run-passes(c,to-list(args[2])) + run-passes(c,to-list(args[2]), outname) else : - run-passes(c,to-list("qabcefghipjklmno")) + run-passes(c,to-list("qabcefghipjklmno"), outname) main() diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 24867612..30898ae6 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1963,8 +1963,14 @@ public defn emit-flo (o:OutputStream, c:Circuit) : emit-module(o, modules(c)[0]) c +public defn emit-flo (pathname:String, c:Circuit) : + val out = FileOutputStream(pathname) + emit-flo(out, c) + close(out) + c + ;============= DRIVER ====================================== -public defn run-passes (c: Circuit, p: List) : +public defn run-passes (c: Circuit, p: List, pathname:String) : var c*:Circuit = c println("Compiling!") if PRINT-CIRCUITS : println("Original Circuit") @@ -1992,12 +1998,5 @@ public defn run-passes (c: Circuit, p: List) : if contains(p,'l') : do-stage("Inline Instances", inline-instances) if contains(p,'m') : do-stage("Split Expressions", split-exp) if contains(p,'n') : do-stage("Real IR", to-real-ir) - if contains(p,'o') : do-stage("To Flo", emit-flo{STANDARD-OUTPUT,_}) + if contains(p,'o') : do-stage("To Flo", emit-flo{pathname,_}) println("Done!") - - - ;; println("Shim for Jonathan's Passes") - ;; c* = shim(c*) - ;; println("Inline Modules") - ;; c* = inline-modules(c*) - ; c* -- cgit v1.2.3 From 2b2f658ffa16ad4c635e037cf77a4db85564da6b Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Mon, 20 Apr 2015 15:52:47 -0700 Subject: better merge --- src/main/stanza/passes.stanza | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 5c4f7ccf..d14da0b5 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1954,12 +1954,6 @@ public defn emit-flo (file:String, c:Circuit) : false c -public defn emit-flo (pathname:String, c:Circuit) : - val out = FileOutputStream(pathname) - emit-flo(out, c) - close(out) - c - ;============= DRIVER ====================================== public defn run-passes (c: Circuit, p: List,file:String) : var c*:Circuit = c -- cgit v1.2.3 From 3f3e42337b04af3befd8a49faf35cfb6a23aa7dd Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Tue, 21 Apr 2015 22:36:20 -0700 Subject: generate correct flo files --- src/main/stanza/passes.stanza | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index e05dfe39..c4e4598b 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1890,7 +1890,7 @@ defn emit! (e:Expression,top:Symbol) : (e:Subfield) : emit-all([exp(e) "/" name(e)], top) (e:Index) : emit-all([exp(e) "/" value(e)], top) (e:Register) : - emit-all(["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) + emit-all(["reg'" prim-width(type(e)) " 1 " value(e)], top) ;; enable(e) (e:ReadPort) : emit-all(["rd'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e)], top) (e:DoPrim) : @@ -1922,6 +1922,16 @@ defn emit! (e:Expression,top:Symbol) : (e) : print-all(["EMIT(" e ")"]) ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right +defn maybe-mov (e:Expression) -> String : + val need-mov? = match(e) : + (e:Ref) : true + (e:UIntValue) : true + (e:SIntValue) : true + (e:Subfield) : true + (e:Index) : true + (e) : false + if need-mov?: "mov " else: "" + defn emit-s (s:Stmt, v:List, top:Symbol) : match(s) : (s:DefWire) : "" @@ -1929,7 +1939,7 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : (s:DefMemory) : val vtype = type(s) as VectorType emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) - (s:DefNode) : emit-all([top "::" name(s) " = " value(s) "\n"], top) + (s:DefNode) : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) (s:Begin) : do(emit-s{_, v, top}, body(s)) (s:Connect) : if loc(s) typeof WritePort : @@ -1939,9 +1949,9 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : else : val n = name(loc(s) as Ref) if contains?(v,n) : - emit-all([n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) + emit-all([top "::" n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) else : - emit-all([top "::" n " = " exp(s) "\n"], top) + emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) (s) : s defn emit-module (m:Module) : -- cgit v1.2.3 From d1bc615be8e214713d5b13a767b2a8abbeeb173a Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Tue, 21 Apr 2015 22:41:21 -0700 Subject: revert --- src/main/stanza/firrtl-main.stanza | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza index fe9b49fa..92bb066f 100644 --- a/src/main/stanza/firrtl-main.stanza +++ b/src/main/stanza/firrtl-main.stanza @@ -21,16 +21,10 @@ defpackage firrtl-main : defn main () : val arg = commandline-arguments() val args = split(arg,' ') - val pathname = args[1] - val lexed = lex-file(pathname) + val lexed = lex-file(args[1]) val c = parse-firrtl(lexed) ;println(c) - val dir = "." ;; could have dir arg - val name = last(split(pathname,'/')) - val basename = split(name,'.')[0] - val outname = string-join([dir "/" basename ".flo"]) - val c* = run-passes(c, to-list(args[2]), outname) - ;; run-passes(c,to-list(args[2])) + run-passes(c,to-list(args[2])) main() -- cgit v1.2.3 From 37c7573dd28a878fe250e1d8ce473fc48aa2fe59 Mon Sep 17 00:00:00 2001 From: jackbackrack Date: Thu, 23 Apr 2015 17:31:08 -0700 Subject: fix more bugs in flo backend --- src/main/stanza/passes.stanza | 48 ++++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index e6206b60..9a259d27 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1759,7 +1759,7 @@ defn split-exp (c:Circuit) : (e:Subfield|DoPrim|Pad|ReadPort|Register|WritePort) : val n* = if n typeof False : gensym(`T) - else : to-symbol $ string-join $ [n as Symbol gensym(`#)] + else : to-symbol $ string-join $ [n as Symbol gensym(`#)] add(v,DefNode(n*,e)) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) (e) : e @@ -1901,8 +1901,17 @@ defn emit-all (es:Streamable, top:Symbol) : (ex) : print(ex) defn emit! (e:Expression,top:Symbol) : + defn greater-op? (op: PrimOp) -> True|False : + contains?([GREATER-OP, GREATER-UU-OP, GREATER-US-OP, GREATER-SU-OP, GREATER-SS-OP], op) + defn greater-eq-op? (op: PrimOp) -> True|False : + contains?([GREATER-EQ-OP, GREATER-EQ-UU-OP, GREATER-EQ-US-OP, GREATER-EQ-SU-OP, GREATER-EQ-SS-OP], op) + defn less-eq-op? (op: PrimOp) -> True|False : + contains?([LESS-EQ-OP, LESS-EQ-UU-OP, LESS-EQ-US-OP, LESS-EQ-SS-OP, LESS-EQ-SS-OP], op) + defn less-op? (op: PrimOp) -> True|False : + contains?([LESS-OP, LESS-UU-OP, LESS-US-OP, LESS-SS-OP, LESS-SS-OP], op) defn cmp-op? (op: PrimOp) -> True|False : - contains?([EQUAL-OP, NEQUAL-OP, GREATER-OP, LESS-EQ-OP, LESS-OP, GREATER-EQ-OP], op) + greater-op?(op) or greater-eq-op?(op) or less-op?(op) or less-eq-op?(op) or + contains?([EQUAL-OP, EQUAL-UU-OP, EQUAL-SS-OP, NEQUAL-OP, NEQUAL-UU-OP, NEQUAL-SS-OP], op) match(e) : (e:Ref) : emit-all([top "::" name(e)], top) (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) @@ -1910,7 +1919,7 @@ defn emit! (e:Expression,top:Symbol) : (e:Subfield) : emit-all([exp(e) "/" name(e)], top) (e:Index) : emit-all([exp(e) "/" value(e)], top) (e:Pad) : - emit-all(["rsh'" prim-width(type(e)) " " value(e) " " width(e)], top) + emit-all(["rsh'" prim-width(type(e)) " " value(e) " " width(e)], top) (e:Register) : emit-all(["reg'" prim-width(type(e)) " 1 " value(e)], top) ;; enable(e) (e:ReadPort) : @@ -1918,10 +1927,10 @@ defn emit! (e:Expression,top:Symbol) : (e:DoPrim) : if cmp-op?(op(e)) : emit-all([flo-op-name(op(e)) "'" prim-width(type(args(e)[0]))], top) - if op(e) == GREATER-OP or op(e) == LESS-EQ-OP : - emit-all([" " args(e)[1] " " args(e)[0]], top) + if greater-op?(op(e)) or less-eq-op?(op(e)) : + emit-all([" " args(e)[1] " " args(e)[0]], top) else : - emit-all([" " args(e)[0] " " args(e)[1]], top) + emit-all([" " args(e)[0] " " args(e)[1]], top) else if op(e) == BIT-SELECT-OP : emit-all([flo-op-name(op(e)) "'1 " args(e)[0] " " consts(e)[0]], top) else if op(e) == BITS-SELECT-OP : @@ -1941,7 +1950,7 @@ defn emit! (e:Expression,top:Symbol) : for const in consts(e) do : print(" ") print(const) - (e) : print-all(["EMIT(" e ")"]) + (e) : error("SHOULDN'T EMIT THIS") ;; print-all(["EMIT(" e ")"]) ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right defn maybe-mov (e:Expression) -> String : @@ -1959,21 +1968,22 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : (s:DefWire) : "" (s:DefInstance) : error("Shouldn't be here") (s:DefMemory) : - val vtype = type(s) as VectorType - emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) - (s:DefNode) : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) + val vtype = type(s) as VectorType + emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) + (s:DefNode) : + if value(s) typeof WritePort : + val e = value(s) as WritePort + val n = gensym(`F) + emit-all([top "::" n " = wr'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e) " " name(s) "\n"], top) + else : + emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) (s:Begin) : do(emit-s{_, v, top}, body(s)) (s:Connect) : - if loc(s) typeof WritePort : - val e = loc(s) as WritePort - val name = gensym(`F) - emit-all([top "::" name " = wr'" prim-width(type(e)) " " enable(e) " " top "::" mem(e) " " index(e) " " exp(s) "\n"], top) + val n = name(loc(s) as Ref) + if contains?(v,n) : + emit-all([top "::" n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) else : - val n = name(loc(s) as Ref) - if contains?(v,n) : - emit-all([top "::" n " = out'" prim-width(type(loc(s))) " " exp(s) "\n"], top) - else : - emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) + emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) (s) : s defn emit-module (m:Module) : -- cgit v1.2.3 From 0224127dc4dba9cf35b0208d32a116b7d33ad925 Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 23 Apr 2015 17:57:01 -0700 Subject: Fixed bug in map where mems were mysteriously turning into regs --- src/main/stanza/ir-utils.stanza | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 86fe56d1..a80c2d7e 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -300,7 +300,7 @@ defmethod map (f: Type -> Type, c:Stmt) -> Stmt : match(c) : (c:DefWire) : DefWire(name(c),f(type(c))) (c:DefRegister) : DefRegister(name(c),f(type(c))) - (c:DefMemory) : DefRegister(name(c),f(type(c))) + (c:DefMemory) : DefMemory(name(c),f(type(c))) (c) : c public defmulti mapr (f: Width -> Width, t:?T&Type) -> T -- cgit v1.2.3 From 6add45d9bb45a179cb7b81f0b4fc3e201019f9cc Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 23 Apr 2015 22:42:32 -0700 Subject: Fixed bug in lowering where the arguments to DoPrim and Pad weren't lowered --- src/main/stanza/ir-utils.stanza | 2 +- src/main/stanza/passes.stanza | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index a80c2d7e..91e49123 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -300,7 +300,7 @@ defmethod map (f: Type -> Type, c:Stmt) -> Stmt : match(c) : (c:DefWire) : DefWire(name(c),f(type(c))) (c:DefRegister) : DefRegister(name(c),f(type(c))) - (c:DefMemory) : DefMemory(name(c),f(type(c))) + (c:DefMemory) : DefMemory(name(c),f(type(c)) as VectorType) (c) : c public defmulti mapr (f: Width -> Width, t:?T&Type) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 50d2831a..6c347dff 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -789,6 +789,12 @@ defn lower (body:Stmt, table:HashTable>>) val exps = expand-expr(exp(e)) val len = num-elems(type(e)) headn(tailn(exps,len * value(e)),len) + (e:Pad) : + val v = key(expand-expr(value(e))[0]) + list(KeyValue(Pad(v,width(e),type(e)),DEFAULT)) + (e:DoPrim) : + val args = for x in args(e) map : key(expand-expr(x)[0]) + list(KeyValue(DoPrim(op(e),args,consts(e),type(e)),DEFAULT)) (e) : list(KeyValue(e, DEFAULT)) ;println-debug(table) -- cgit v1.2.3 From 1652c3cf8329246fa372513fb0d2bdf53ddd227f Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 12:31:12 -0700 Subject: Fixed performance bug in expand-when where equality between the consequence and alternate were always assumed different, causing a huge blow-up in logic --- src/main/stanza/passes.stanza | 53 +++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 6c347dff..4cd494df 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1011,20 +1011,25 @@ val one = UIntValue(1,IntWidth(1)) defmethod equal? (e1:Expression,e2:Expression) -> True|False : match(e1,e2) : (e1:UIntValue,e2:UIntValue) : - if value(e1) == value(e2) : - match(width(e1), width(e2)) : - (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) - (w1,w2) : false + if value(e1) == value(e2) : width(e1) == width(e2) else : false (e1:SIntValue,e2:SIntValue) : - if value(e1) == value(e2) : - match(width(e1), width(e2)) : - (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) + if value(e1) == value(e2) : width(e1) == width(e2) else : false (e1:WRef,e2:WRef) : name(e1) == name(e2) ;(e1:DoPrim,e2:DoPrim) : TODO (e1:WRegInit,e2:WRegInit) : reg(e1) == reg(e2) and name(e1) == name(e2) (e1:WSubfield,e2:WSubfield) : name(e1) == name(e2) + (e1:Pad,e2:Pad) : width(e1) == width(e2) and value(e1) == value(e2) + (e1:DoPrim,e2:DoPrim) : + var are-equal? = op(e1) == op(e2) + for (x in args(e1),y in args(e2)) do : + if not x == y : + are-equal? = false + for (x in consts(e1),y in consts(e2)) do : + if not x == y : + are-equal? = false + are-equal? (e1,e2) : false defn AND (e1:Expression,e2:Expression) -> Expression : @@ -1292,7 +1297,9 @@ defn build-tables (s:Stmt, build-tables(alt(s),assign-a,kinds,decs,stmts) for i in get-unique-keys(list(assign-c,assign-a)) do : assign[i] = match(get?(assign-c,i,false),get?(assign-a,i,false)) : ;TODO add to syntax highlighting - (c:SymbolicValue,a:SymbolicValue) : SVMux(pred(s),c,a) + (c:SymbolicValue,a:SymbolicValue) : + if c == a : c + else : SVMux(pred(s),c,a) (c:SymbolicValue,a:False) : if kinds[i] typeof WireKind|InstanceKind|NodeKind : c else : SVMux(pred(s),c,SVNul()) @@ -1300,12 +1307,12 @@ defn build-tables (s:Stmt, if kinds[i] typeof WireKind|InstanceKind|NodeKind : a else : SVMux(pred(s),SVNul(),a) (c:False,a:False) : error("Shouldn't be here") - ;println-debug("TABLE-C") - ;for x in assign-c do : println-debug(x) - ;println-debug("TABLE-A") - ;for x in assign-a do : println-debug(x) - ;println-debug("TABLE") - ;for x in assign do : println-debug(x) + println-debug("TABLE-C") + for x in assign-c do : println-debug(x) + println-debug("TABLE-A") + for x in assign-a do : println-debug(x) + println-debug("TABLE") + for x in assign do : println-debug(x) (s:Connect) : val key* = match(loc(s)) : (e:WRef) : name(e) @@ -1328,18 +1335,19 @@ defn expand-whens (m:Module) -> Module : stmts[name(p)] = DefWire(name(p),type(p)) build-tables(body(m),assign,kinds,decs,stmts) + for x in assign do : assign[key(x)] = optimize(value(x)) val enables = get-enables(assign,kinds) for x in enables do : enables[key(x)] = optimize(value(x)) - ;println-debug("Assigns") - ;for x in assign do : println-debug(x) - ;println-debug("Kinds") - ;for x in kinds do : println-debug(x) - ;println-debug("Decs") - ;for x in decs do : println-debug(x) - ;println-debug("Enables") - ;for x in enables do : println-debug(x) + println-debug("Assigns") + for x in assign do : println-debug(x) + println-debug("Kinds") + for x in kinds do : println-debug(x) + println-debug("Decs") + for x in decs do : println-debug(x) + println-debug("Enables") + for x in enables do : println-debug(x) Module(name(m),ports(m),expand-whens(assign,kinds,stmts,decs,enables)) @@ -1404,6 +1412,7 @@ defmethod equal? (w1:Width,w2:Width) -> True|False : if not contains?(args(w2),w) : ret(false) ret(true) (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) + (w1:UnknownWidth,w2:UnknownWidth) : true (w1,w2) : false defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : if a typeof Int and b typeof Int : f(a as Int, b as Int) -- cgit v1.2.3 From bd8b9669d1cdc4898be9d38ca9c492866d927d77 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 14:46:44 -0700 Subject: Fixed width inference bug where later constraints on the output width were not propogating to the input widths, for primops --- src/main/stanza/primop.stanza | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 14589135..a1e9633f 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -248,12 +248,12 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim : BIT-XOR-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u()) public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : - defn all-equal (ls:List) -> Width : - if length(ls) == 1 : width!(ls[0]) + defn all-equal (ls:List) -> Width : + if length(ls) == 1 : (ls[0]) else : - val m = MaxWidth(map(width!,ls)) + val m = MaxWidth(ls) for (l in ls) do : - add(v,WGeq(width!(l),m)) + add(v,WGeq(l,m)) m ;defn new-width (w:Width) -> Width: ; val w* = VarWidth(gensym(`w)) @@ -275,9 +275,11 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : val all-args-not-equal = list(MUX-UU-OP,MUX-SS-OP,CONCAT-OP) ;val consts-gte-args = list(PAD-U-OP,PAD-S-OP) + + val w-var = VarWidth(gensym(`w)) val w* = if not contains?(all-args-not-equal,op(e)) : - val max-args-w = all-equal(args(e)) + val max-args-w = all-equal(List(w-var,map(width!,args(e)))) switch {op(e) == _} : ADD-UU-OP : PlusWidth(max-args-w,IntWidth(1)) ADD-US-OP : PlusWidth(max-args-w,IntWidth(1)) @@ -347,14 +349,13 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : switch {op(e) == _} : MUX-UU-OP : add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(tail(args(e))) + all-equal(List(w-var,tail(map(width!,args(e))))) MUX-SS-OP : add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(tail(args(e))) + all-equal(List(w-var,tail(map(width!,args(e))))) CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) - val w-var = VarWidth(gensym(`w)) add(v,WGeq(w-var,w*)) match(type(e)) : (t:UIntType) : UIntType(w-var) -- cgit v1.2.3 From 2006198a53328e3898bcbe69429b751c065ea802 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 14:58:38 -0700 Subject: Incorrectly propagated width constraint for non-muxes. This is only true for muxes --- src/main/stanza/primop.stanza | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index a1e9633f..a6b42e7c 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -279,7 +279,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : val w-var = VarWidth(gensym(`w)) val w* = if not contains?(all-args-not-equal,op(e)) : - val max-args-w = all-equal(List(w-var,map(width!,args(e)))) + val max-args-w = all-equal(map(width!,args(e))) switch {op(e) == _} : ADD-UU-OP : PlusWidth(max-args-w,IntWidth(1)) ADD-US-OP : PlusWidth(max-args-w,IntWidth(1)) -- cgit v1.2.3 From 5a2a495ce88eec9e2e79cfbfe7f5548cede25874 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 24 Apr 2015 16:58:06 -0700 Subject: Updated TODO. Added backwards with prop for as and bits --- src/main/stanza/primop.stanza | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index a6b42e7c..e88a6b8e 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -329,20 +329,12 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : PAD-S-OP : IntWidth(consts(e)[0]) NEG-U-OP : IntWidth(1) NEG-S-OP : IntWidth(1) - AS-UINT-U-OP : max-args-w - AS-UINT-S-OP : max-args-w - AS-SINT-U-OP : max-args-w - AS-SINT-S-OP : max-args-w SHIFT-LEFT-U-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-LEFT-S-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-U-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) SHIFT-RIGHT-S-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) CONVERT-U-OP : PlusWidth(max-args-w,IntWidth(1)) CONVERT-S-OP : max-args-w - BIT-NOT-OP : max-args-w - BIT-AND-OP : max-args-w - BIT-OR-OP : max-args-w - BIT-XOR-OP : max-args-w BIT-SELECT-OP : IntWidth(1) BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) else : @@ -355,6 +347,17 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector) -> Type : all-equal(List(w-var,tail(map(width!,args(e))))) CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) + BIT-NOT-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-AND-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-OR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + BIT-XOR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-UINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) + AS-SINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) add(v,WGeq(w-var,w*)) match(type(e)) : -- cgit v1.2.3