From c6c509d623e5e64e021fa311018b8ace2f3f8969 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Wed, 7 Aug 2019 16:33:45 -0700
Subject: Check mems for legal latencies; ban zero write latency. (#1147)

* Check mems for legal latencies; ban zero write latency.

* Trigger
---
 src/main/scala/firrtl/passes/Checks.scala  |  4 ++++
 src/test/scala/firrtlTests/CheckSpec.scala | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 471fe216..4bcfad9c 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -27,6 +27,8 @@ trait CheckHighFormLike {
     s"$info: [module $mname] Memory $name has not been properly lowered from Chirrtl IR.")
   class MemWithFlipException(info: Info, mname: String, name: String) extends PassException(
     s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
+  class IllegalMemLatencyException(info: Info, mname: String, name: String) extends PassException(
+    s"$info: [module $mname] Memory $name must have non-negative read latency and positive write latency.")
   class RegWithFlipException(info: Info, mname: String, name: String) extends PassException(
     s"$info: [module $mname] Register $name cannot be a bundle type with flips.")
   class InvalidAccessException(info: Info, mname: String) extends PassException(
@@ -191,6 +193,8 @@ trait CheckHighFormLike {
           if (reset.tpe == AsyncResetType && !init.isInstanceOf[Literal])
             errors.append(new NonLiteralAsyncResetValueException(info, mname, name, init.serialize))
         case sx: DefMemory =>
+          if (sx.readLatency < 0 || sx.writeLatency <= 0)
+            errors.append(new IllegalMemLatencyException(info, mname, sx.name))
           if (hasFlip(sx.dataType))
             errors.append(new MemWithFlipException(info, mname, sx.name))
           if (sx.depth <= 0)
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 93bc2cab..54dc60ab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -41,6 +41,25 @@ class CheckSpec extends FlatSpec with Matchers {
     }
   }
 
+  "Memories with zero write latency" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    mem m :
+        |      data-type => UInt<32>
+        |      depth => 32
+        |      read-latency => 0
+        |      write-latency => 0""".stripMargin
+    intercept[CheckHighForm.IllegalMemLatencyException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
   "Registers with flip in the type" should "throw an exception" in {
     val input =
       """circuit Unit :
-- 
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