From c48c691e94afe4919c20fa588a9897316c572447 Mon Sep 17 00:00:00 2001
From: Jack
Date: Tue, 23 Feb 2016 00:57:09 -0800
Subject: Add rocket regression, just runs rocket.fir through Verilog compiler
 and compares to expected Verilog. Uses ScalaTest. Should be eventually
 replaced with actual simulation of rocket-chip

---
 src/test/resources/regress               |  1 +
 src/test/scala/firrtlTests/Regress.scala | 23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+)
 create mode 120000 src/test/resources/regress
 create mode 100644 src/test/scala/firrtlTests/Regress.scala

(limited to 'src')

diff --git a/src/test/resources/regress b/src/test/resources/regress
new file mode 120000
index 00000000..3691434b
--- /dev/null
+++ b/src/test/resources/regress
@@ -0,0 +1 @@
+../../../regress
\ No newline at end of file
diff --git a/src/test/scala/firrtlTests/Regress.scala b/src/test/scala/firrtlTests/Regress.scala
new file mode 100644
index 00000000..49c95590
--- /dev/null
+++ b/src/test/scala/firrtlTests/Regress.scala
@@ -0,0 +1,23 @@
+
+package firrtlTests
+
+import org.scalatest._
+
+import firrtl._
+import java.io._
+import scala.io.Source
+
+class RocketRegressionSpec extends FlatSpec with Matchers {
+
+  // This test is temporary until we move to simulation-based testing
+  "CHIRRTL Rocket" should "match expected Verilog" in {
+    val firrtlSource = Source.fromURL(getClass.getResource("/regress/rocket.fir"))
+    val highCircuit = firrtl.Parser.parse("rocket.fir", firrtlSource.getLines)
+    val verilogSW = new StringWriter()
+    VerilogCompiler.run(highCircuit, verilogSW)
+
+    val goldenVerilog = Source.fromURL(getClass.getResource("/regress/rocket-golden.v"))
+    
+    verilogSW.toString shouldEqual goldenVerilog.mkString 
+  }
+}
-- 
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