From c450cf974484d4896910c44166481d0849219751 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 6 Nov 2019 16:37:59 -0800
Subject: Add check for multiple sources for same wiring pin (#1191)

---
 .../scala/firrtl/passes/wiring/WiringTransform.scala |  8 +++++++-
 src/test/scala/firrtlTests/WiringTests.scala         | 20 ++++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index c42d1f8b..31030375 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -54,11 +54,17 @@ class WiringTransform extends Transform {
       case p =>
         val sinks = mutable.HashMap[String, Seq[Named]]()
         val sources = mutable.HashMap[String, ComponentName]()
-        p.foreach {
+        val errors = p.flatMap {
           case SinkAnnotation(m, pin) =>
             sinks(pin) = sinks.getOrElse(pin, Seq.empty) :+ m
+            None
           case SourceAnnotation(c, pin) =>
+            val res = if (sources.contains(pin)) Some(pin) else None
             sources(pin) = c
+            res
+        }
+        if (errors.nonEmpty) {
+          throw WiringException(s"Multiple sources specified for wiring pin(s): " + errors.distinct.mkString(", "))
         }
         (sources.size, sinks.size) match {
           case (0, p) => state
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index ec69c39f..b2793494 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -809,4 +809,24 @@ class WiringTests extends FirrtlFlatSpec {
     val wiringPass = new Wiring(wiSeq)
     executeTest(input, check, passes :+ wiringPass)
   }
+
+  it should "error when there are multiple sources for the same pin" in {
+    val sink = ComponentName("s", ModuleName("Top", CircuitName("Top")))
+    val source1 = ComponentName("r", ModuleName("Top", CircuitName("Top")))
+    val source2 = ComponentName("r2", ModuleName("Top", CircuitName("Top")))
+    val annos = Seq(SourceAnnotation(source1, "pin"),
+                    SourceAnnotation(source2, "pin"),
+                    SinkAnnotation(sink, "pin"))
+    val input =
+      """|circuit Top :
+         |  module Top :
+         |    input clock: Clock
+         |    wire s: UInt<5>
+         |    reg r: UInt<5>, clock
+         |    reg r2: UInt<5>, clock
+         |""".stripMargin
+    a [WiringException] shouldBe thrownBy {
+      executeTest(input, "", passes :+ new WiringTransform, annos)
+    }
+  }
 }
-- 
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