From c241ed5e77a84634c5d4729b44b07436c0472a42 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 17:15:34 -0800
Subject: Moved inst declarations after other declarations

---
 src/main/stanza/passes.stanza | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 150abe32..30527af8 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2383,6 +2383,7 @@ defn emit-verilog (m:InModule) -> Module :
 
    val portdefs = Vector<Streamable>()
    val declares = Vector<Streamable>()
+   val instdeclares = Vector<Streamable>()
    val assigns = Vector<Streamable>()
    val at-clock = HashTable<Expression,Vector<Streamable>>(exp-hash)
    val initials = Vector<Streamable>()
@@ -2432,12 +2433,12 @@ defn emit-verilog (m:InModule) -> Module :
       val index = WRef(`initvar,UnknownType(),ExpKind(),UNKNOWN-GENDER)
       add(initials,[tab WSubAccess(wref(n,t),index,UnknownType(),FEMALE), " = " rand-string(t) ";"])
    defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) :
-      add(declares,[m " " n " ("])
+      add(instdeclares,[m " " n " ("])
       for (e in es,i in 0 to false) do :
          val s = [tab "." remove-root(e) "(" lowered-name(e) ")"]
-         if i != length(es) - 1 : add(declares,[s ","])
-         else : add(declares,s)
-      add(declares,[");"])
+         if i != length(es) - 1 : add(instdeclares,[s ","])
+         else : add(instdeclares,s)
+      add(instdeclares,[");"])
       for e in es do :
          declare(`wire,lowered-name(e),type(e))
          val e* = WRef(lowered-name(e),type(e),kind(e),gender(e))
@@ -2614,6 +2615,9 @@ defn emit-verilog (m:InModule) -> Module :
 
       if !empty?(declares) :
          for x in declares do : emit([tab x])
+
+      if !empty?(instdeclares) :
+         for x in instdeclares do : emit([tab x])
       
       if !empty?(assigns) :
          for x in assigns do : emit([tab x])
-- 
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