From b9bf7ad196a203526977c0e299b60948be6b29c6 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Wed, 27 Apr 2016 00:29:05 -0700
Subject: Remove nested AND in creation of readwrite ports for mems.

Fixes #147
---
 src/main/scala/firrtl/Emitter.scala | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 5414053a..17cb9d50 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -554,7 +554,13 @@ class VerilogEmitter extends Emitter {
                   val rmem_port = WSubAccess(mem,raddrx,s.data_type,UNKNOWNGENDER)
                   assign(rdata,rmem_port)
                   val wmem_port = WSubAccess(mem,waddrx,s.data_type,UNKNOWNGENDER)
-                  update(wmem_port,datax,clk,AND(AND(enx,maskx),wmode))
+
+                  val tempName = namespace.newTemp
+                  val tempExp = AND(enx,maskx)
+                  declare("wire", tempName, tpe(tempExp))
+                  val tempWRef = wref(tempName, tpe(tempExp))
+                  assign(tempWRef, tempExp)
+                  update(wmem_port,datax,clk,AND(tempWRef,wmode))
                }
             }
             case (s:Begin) => s map (build_streams)
-- 
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