From aa571e1d4f76d095344a9deed28dfa70f704fa75 Mon Sep 17 00:00:00 2001
From: Leway Colin
Date: Tue, 9 Jul 2019 01:41:02 +0800
Subject: Remove some warnings (#1118)

---
 src/main/scala/firrtl/Emitter.scala                      |  4 +---
 src/main/scala/firrtl/PrimOps.scala                      |  1 -
 src/main/scala/firrtl/Utils.scala                        | 16 ++++++++--------
 src/main/scala/firrtl/annotations/Target.scala           |  3 +--
 src/main/scala/firrtl/graph/DiGraph.scala                |  6 +++---
 src/main/scala/firrtl/graph/EulerTour.scala              |  4 ++--
 src/main/scala/firrtl/passes/Checks.scala                |  2 +-
 src/main/scala/firrtl/passes/InferTypes.scala            |  1 -
 src/main/scala/firrtl/passes/InferWidths.scala           |  1 -
 src/main/scala/firrtl/passes/Inline.scala                |  2 +-
 src/main/scala/firrtl/passes/memlib/DecorateMems.scala   |  4 ----
 src/main/scala/firrtl/passes/memlib/InferReadWrite.scala |  2 --
 src/main/scala/firrtl/passes/memlib/MemIR.scala          |  1 -
 .../scala/firrtl/passes/memlib/VerilogMemDelays.scala    |  4 ++--
 src/main/scala/firrtl/passes/wiring/Wiring.scala         | 12 ++++++------
 src/main/scala/firrtl/passes/wiring/WiringUtils.scala    |  4 ++--
 src/main/scala/firrtl/transforms/Dedup.scala             |  1 -
 src/main/scala/firrtl/transforms/Flatten.scala           |  3 +--
 .../firrtl/transforms/RemoveKeywordCollisions.scala      |  1 -
 src/main/scala/firrtl/transforms/TopWiring.scala         | 10 ++++------
 src/main/scala/logger/Logger.scala                       |  2 +-
 21 files changed, 33 insertions(+), 51 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index e23becdb..8e6408fe 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -673,7 +673,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
       // Turn types into strings, all ports must be GroundTypes
       val tpes = m.ports map {
         case Port(_, _, _, tpe: GroundType) => stringify(tpe)
-        case port: Port => error("Trying to emit non-GroundType Port $port")
+        case port: Port => error(s"Trying to emit non-GroundType Port $port")
       }
 
       // dirs are already padded
@@ -767,9 +767,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
           for (r <- sx.readers) {
             val data = memPortField(sx, r, "data")
             val addr = memPortField(sx, r, "addr")
-            val en = memPortField(sx, r, "en")
             // Ports should share an always@posedge, so can't have intermediary wire
-            val clk = netlist(memPortField(sx, r, "clk"))
 
             declare("wire", LowerTypes.loweredName(data), data.tpe, sx.info)
             declare("wire", LowerTypes.loweredName(addr), addr.tpe, sx.info)
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index 4d60bae7..0f1ecff7 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -122,7 +122,6 @@ object PrimOps extends LazyLogging {
     //println-all(["Inferencing primop type: " e])
     def t1 = e.args.head.tpe
     def t2 = e.args(1).tpe
-    def t3 = e.args(2).tpe
     def w1 = getWidth(e.args.head.tpe)
     def w2 = getWidth(e.args(1).tpe)
     def p1 = t1 match { case FixedType(w, p) => p } //Intentional
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index b7073f70..72003608 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -114,13 +114,13 @@ object fromBits {
                       rhs: Expression,
                       offset: BigInt): (BigInt, Seq[Statement]) =
     lhst match {
-      case t: VectorType => (0 until t.size foldLeft (offset, Seq[Statement]())) {
+      case t: VectorType => (0 until t.size foldLeft( (offset, Seq[Statement]()) )) {
         case ((curOffset, stmts), i) =>
           val subidx = WSubIndex(lhs, i, t.tpe, UNKNOWNGENDER)
           val (tmpOffset, substmts) = getPart(subidx, t.tpe, rhs, curOffset)
           (tmpOffset, stmts ++ substmts)
       }
-      case t: BundleType => (t.fields foldRight (offset, Seq[Statement]())) {
+      case t: BundleType => (t.fields foldRight( (offset, Seq[Statement]()) )) {
         case (f, (curOffset, stmts)) =>
           val subfield = WSubField(lhs, f.name, f.tpe, UNKNOWNGENDER)
           val (tmpOffset, substmts) = getPart(subfield, f.tpe, rhs, curOffset)
@@ -303,7 +303,7 @@ object Utils extends LazyLogging {
      t match {
        case (_: GroundType) => f
        case (tx: BundleType) =>
-         val (_, flip) = tx.fields.foldLeft(i, None: Option[Orientation]) {
+         val (_, flip) = tx.fields.foldLeft( (i, None: Option[Orientation]) ) {
            case ((n, ret), x) if n < get_size(x.tpe) => ret match {
              case None => (n, Some(get_flip(x.tpe, n, times(x.flip, f))))
              case Some(_) => (n, ret)
@@ -312,7 +312,7 @@ object Utils extends LazyLogging {
          }
          flip.get
        case (tx: VectorType) =>
-         val (_, flip) = (0 until tx.size).foldLeft(i, None: Option[Orientation]) {
+         val (_, flip) = (0 until tx.size).foldLeft( (i, None: Option[Orientation]) ) {
            case ((n, ret), x) if n < get_size(tx.tpe) => ret match {
              case None => (n, Some(get_flip(tx.tpe, n, f)))
              case Some(_) => (n, ret)
@@ -453,10 +453,10 @@ object Utils extends LazyLogging {
       case (_: AnalogType, _: AnalogType) => if (flip1 == flip2) Seq((0, 0)) else Nil
       case (t1x: BundleType, t2x: BundleType) =>
         def emptyMap = Map[String, (Type, Orientation, Int)]()
-        val t1_fields = t1x.fields.foldLeft(emptyMap, 0) { case ((map, ilen), f1) =>
-          (map + (f1.name ->(f1.tpe, f1.flip, ilen)), ilen + get_size(f1.tpe))
+        val t1_fields = t1x.fields.foldLeft( (emptyMap, 0) ) { case ((map, ilen), f1) =>
+          (map + (f1.name ->( (f1.tpe, f1.flip, ilen) )), ilen + get_size(f1.tpe))
         }._1
-        t2x.fields.foldLeft(Seq[(Int, Int)](), 0) { case ((points, jlen), f2) =>
+        t2x.fields.foldLeft( (Seq[(Int, Int)](), 0) ) { case ((points, jlen), f2) =>
           t1_fields get f2.name match {
             case None => (points, jlen + get_size(f2.tpe))
             case Some((f1_tpe, f1_flip, ilen)) =>
@@ -468,7 +468,7 @@ object Utils extends LazyLogging {
         }._1
       case (t1x: VectorType, t2x: VectorType) =>
         val size = math.min(t1x.size, t2x.size)
-        (0 until size).foldLeft(Seq[(Int, Int)](), 0, 0) { case ((points, ilen, jlen), _) =>
+        (0 until size).foldLeft( (Seq[(Int, Int)](), 0, 0) ) { case ((points, ilen, jlen), _) =>
           val ls = get_valid_points(t1x.tpe, t2x.tpe, flip1, flip2)
           (points ++ (ls map { case (x, y) => (x + ilen, y + jlen) }),
             ilen + get_size(t1x.tpe), jlen + get_size(t2x.tpe))
diff --git a/src/main/scala/firrtl/annotations/Target.scala b/src/main/scala/firrtl/annotations/Target.scala
index 0247b66c..72864957 100644
--- a/src/main/scala/firrtl/annotations/Target.scala
+++ b/src/main/scala/firrtl/annotations/Target.scala
@@ -380,7 +380,6 @@ trait IsMember extends CompleteTarget {
 
   /** @return List of local Instance Targets refering to each instance/ofModule in this member's path */
   def pathAsTargets: Seq[InstanceTarget] = {
-    val targets = mutable.ArrayBuffer[InstanceTarget]()
     path.foldLeft((module, Vector.empty[InstanceTarget])) {
       case ((m, vec), (Instance(i), OfModule(o))) =>
         (o, vec :+ InstanceTarget(circuit, m, Nil, i, o))
@@ -651,7 +650,7 @@ case class InstanceTarget(circuit: String,
     }
   }
 
-  override def asPath: Seq[(Instance, OfModule)] = path :+ (Instance(instance), OfModule(ofModule))
+  override def asPath: Seq[(Instance, OfModule)] = path :+( (Instance(instance), OfModule(ofModule)) )
 
   override def pathlessTarget: InstanceTarget = InstanceTarget(circuit, encapsulatingModule, Nil, instance, ofModule)
 
diff --git a/src/main/scala/firrtl/graph/DiGraph.scala b/src/main/scala/firrtl/graph/DiGraph.scala
index 3fa0ade7..cc100441 100644
--- a/src/main/scala/firrtl/graph/DiGraph.scala
+++ b/src/main/scala/firrtl/graph/DiGraph.scala
@@ -78,7 +78,7 @@ class DiGraph[T] private[graph] (private[graph] val edges: LinkedHashMap[T, Link
     val unmarked = new mutable.LinkedHashSet[T]
     val tempMarked = new mutable.LinkedHashSet[T]
 
-    case class LinearizeFrame[T](v: T, expanded: Boolean)
+    case class LinearizeFrame[A](v: A, expanded: Boolean)
     val callStack = mutable.Stack[LinearizeFrame[T]]()
 
     unmarked ++= seed.getOrElse(getVertices)
@@ -239,7 +239,7 @@ class DiGraph[T] private[graph] (private[graph] val edges: LinkedHashMap[T, Link
      * created on the last iteration where the current frame was
      * active is sufficient to track the position.
      */
-    class StrongConnectFrame[T](val v: T, val edgeIter: Iterator[T], var childCall: Option[T] = None)
+    class StrongConnectFrame[A](val v: A, val edgeIter: Iterator[A], var childCall: Option[A] = None)
     val callStack = new mutable.Stack[StrongConnectFrame[T]]
 
     for (node <- getVertices) {
@@ -331,7 +331,7 @@ class DiGraph[T] private[graph] (private[graph] val edges: LinkedHashMap[T, Link
   private def filterEdges(vprime: Set[T]): LinkedHashMap[T, LinkedHashSet[T]] = {
     def filterNodeSet(s: LinkedHashSet[T]): LinkedHashSet[T] = s.filter({ case (k) => vprime.contains(k) })
     def filterAdjacencyLists(m: LinkedHashMap[T, LinkedHashSet[T]]): LinkedHashMap[T, LinkedHashSet[T]] = m.map({ case (k, v) => (k, filterNodeSet(v)) })
-    var eprime: LinkedHashMap[T, LinkedHashSet[T]] = edges.filter({ case (k, v) => vprime.contains(k) })
+    val eprime: LinkedHashMap[T, LinkedHashSet[T]] = edges.filter({ case (k, v) => vprime.contains(k) })
     filterAdjacencyLists(eprime)
   }
 
diff --git a/src/main/scala/firrtl/graph/EulerTour.scala b/src/main/scala/firrtl/graph/EulerTour.scala
index 29c97b20..1e3b02ca 100644
--- a/src/main/scala/firrtl/graph/EulerTour.scala
+++ b/src/main/scala/firrtl/graph/EulerTour.scala
@@ -112,7 +112,7 @@ class EulerTour[T](r: Map[T, Int], e: Seq[T], h: Seq[Int]) {
     * entry in the range is different from the last by only +-1
     */
   private def constructTableLookups(n: Int): Array[Array[Array[Int]]] = {
-    def sortSeqSeq[T <: Int](x: Seq[T], y: Seq[T]): Boolean = {
+    def sortSeqSeq[A <: Int](x: Seq[A], y: Seq[A]): Boolean = {
       if (x(0) != y(0)) x(0) < y(0) else sortSeqSeq(x.tail, y.tail)
     }
 
@@ -122,7 +122,7 @@ class EulerTour[T](r: Map[T, Int], e: Seq[T], h: Seq[Int]) {
       .sortWith(sortSeqSeq)
       .map(_.foldLeft(Seq(0))((h, pm) => (h.head + pm) +: h).reverse)
       .map{ a =>
-        var tmp = Array.ofDim[Int](m, m)
+        val tmp = Array.ofDim[Int](m, m)
         for (i <- 0 to size; j <- i to size) yield {
           val window = a.slice(i, j + 1)
           tmp(i)(j) = window.indexOf(window.min) + i }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index e28116ea..c1415b19 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -397,7 +397,7 @@ object CheckTypes extends Pass {
         case (_: AnalogType, _: AnalogType) => true
         case (t1: BundleType, t2: BundleType) =>
           val t1_fields = (t1.fields foldLeft Map[String, (Type, Orientation)]())(
-            (map, f1) => map + (f1.name -> (f1.tpe, f1.flip)))
+            (map, f1) => map + (f1.name ->( (f1.tpe, f1.flip) )))
           t2.fields forall (f2 =>
             t1_fields get f2.name match {
               case None => true
diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index 24482076..288b62ba 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -78,7 +78,6 @@ object CInferTypes extends Pass {
   type TypeMap = collection.mutable.LinkedHashMap[String, Type]
 
   def run(c: Circuit): Circuit = {
-    val namespace = Namespace()
     val mtypes = (c.modules map (m => m.name -> module_type(m))).toMap
 
     def infer_types_e(types: TypeMap)(e: Expression) : Expression =
diff --git a/src/main/scala/firrtl/passes/InferWidths.scala b/src/main/scala/firrtl/passes/InferWidths.scala
index 79dda51b..cf6f2ae0 100644
--- a/src/main/scala/firrtl/passes/InferWidths.scala
+++ b/src/main/scala/firrtl/passes/InferWidths.scala
@@ -288,7 +288,6 @@ class InferWidths extends Transform with ResolvedAnnotationPaths {
     def get_constraints_s(s: Statement): Unit = {
       s map get_constraints_declared_type match {
         case (s: Connect) =>
-          val n = get_size(s.loc.tpe)
           val locs = create_exps(s.loc)
           val exps = create_exps(s.expr)
           v ++= locs.zip(exps).flatMap { case (locx, expx) =>
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 986252ea..7f8913c6 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -45,7 +45,7 @@ class InlineInstances extends Transform with RegisteredTransform {
       helpValueName = Some("<circuit>[.<module>[.<instance>]][,...]") ) )
 
    private def collectAnns(circuit: Circuit, anns: Iterable[Annotation]): (Set[ModuleName], Set[ComponentName]) =
-     anns.foldLeft(Set.empty[ModuleName], Set.empty[ComponentName]) {
+     anns.foldLeft( (Set.empty[ModuleName], Set.empty[ComponentName]) ) {
        case ((modNames, instNames), ann) => ann match {
          case InlineAnnotation(CircuitName(c)) =>
            (circuit.modules.collect {
diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
index aa20e41e..412098fd 100644
--- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
+++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala
@@ -3,8 +3,6 @@
 package firrtl
 package passes
 package memlib
-import annotations._
-import wiring._
 
 class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform {
   def inputForm = MidForm
@@ -14,10 +12,8 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform
     case Some(r) =>
       import CustomYAMLProtocol._
       val configs = r.parse[Config]
-      val cN = CircuitName(state.circuit.main)
       val oldAnnos = state.annotations
       val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { case ((annos, pins), config) =>
-        val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), config.pin.name)
         (annos, pins :+ config.pin.name)
       }
       state.copy(annotations = PinAnnotation(pins.toSeq) +: as)
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 1663efaa..44f45985 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -85,8 +85,6 @@ object InferReadWritePass extends Pass {
                          (s: Statement): Statement = s match {
     // infer readwrite ports only for non combinational memories
     case mem: DefMemory if mem.readLatency > 0 =>
-      val ut = UnknownType
-      val ug = UNKNOWNGENDER
       val readers = new PortSet
       val writers = new PortSet
       val readwriters = collection.mutable.ArrayBuffer[String]()
diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala
index aa60fca0..2379feab 100644
--- a/src/main/scala/firrtl/passes/memlib/MemIR.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala
@@ -3,7 +3,6 @@
 package firrtl.passes
 package memlib
 
-import firrtl._
 import firrtl.ir._
 
 object DefAnnotatedMemory {
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index f06ca61a..10bcadfb 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -41,7 +41,7 @@ object VerilogMemDelays extends Pass {
         if !ports(newName)
       } yield newName).head
       val rwMap = (sx.readwriters map (rw =>
-        rw -> (newPortName(rw, "r"), newPortName(rw, "w")))).toMap
+        rw ->( (newPortName(rw, "r"), newPortName(rw, "w")) ))).toMap
       // 1. readwrite ports are split into read & write ports
       // 2. memories are transformed into combinational
       //    because latency pipes are added for longer latencies
@@ -59,7 +59,7 @@ object VerilogMemDelays extends Pass {
         // 2) pipe registers and connects
         val node = DefNode(NoInfo, namespace.newTemp, netlist(e))
         val wref = WRef(node.name, e.tpe, NodeKind, MALE)
-        ((0 until n) foldLeft (wref, Seq[Statement](node))){case ((ex, stmts), i) =>
+        ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) =>
           val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i"
           val exx = WRef(name, e.tpe, RegKind, ug)
           (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 447a5a6a..c074168b 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -97,7 +97,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
           val from = s"${portNames(pm)}"
           meta(pm) = meta(pm).copy(
             addPortOrWire = Some((portNames(pm), DecWire)),
-            cons = (meta(pm).cons :+ (to, from)).distinct
+            cons = (meta(pm).cons :+( (to, from) )).distinct
           )
           meta(cm) = meta(cm).copy(
             addPortOrWire = Some((portNames(cm), DecInput))
@@ -115,7 +115,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
             val from = s"$ci.${portNames(cm)}"
             meta(pm) = meta(pm).copy(
               addPortOrWire = Some((portNames(pm), DecWire)),
-              cons = (meta(pm).cons :+ (to, from)).distinct
+              cons = (meta(pm).cons :+( (to, from) )).distinct
             )
           }
       }
@@ -126,7 +126,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
           val from = s"${portNames(m)}"
           sinkComponents(m).foreach( to =>
             meta(m) = meta(m).copy(
-              cons = (meta(m).cons :+ (to, from)).distinct
+              cons = (meta(m).cons :+( (to, from) )).distinct
             )
           )
         }
@@ -137,7 +137,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
         val to = s"${portNames(m)}"
         val from = compName
         meta(m) = meta(m).copy(
-          cons = (meta(m).cons :+ (to, from)).distinct
+          cons = (meta(m).cons :+( (to, from) )).distinct
         )
       }
 
@@ -147,7 +147,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
           val to = s"${portNames(pm)}"
           val from = s"$ci.${portNames(cm)}"
           meta(pm) = meta(pm).copy(
-            cons = (meta(pm).cons :+ (to, from)).distinct
+            cons = (meta(pm).cons :+( (to, from) )).distinct
           )
           meta(cm) = meta(cm).copy(
             addPortOrWire = Some((portNames(cm), DecOutput))
@@ -163,7 +163,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
             val to = s"$ci.${portNames(cm)}"
             val from = s"${portNames(pm)}"
             meta(pm) = meta(pm).copy(
-              cons = (meta(pm).cons :+ (to, from)).distinct
+              cons = (meta(pm).cons :+( (to, from) )).distinct
             )
           }
         }
diff --git a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
index 45cf1212..9eed358f 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringUtils.scala
@@ -85,9 +85,9 @@ object WiringUtils {
     val childrenMap = new ChildrenMap()
     def getChildren(mname: String)(s: Statement): Unit = s match {
       case s: WDefInstance =>
-        childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module)
+        childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) )
       case s: DefInstance =>
-        childrenMap(mname) = childrenMap(mname) :+ (s.name, s.module)
+        childrenMap(mname) = childrenMap(mname) :+( (s.name, s.module) )
       case s => s.foreach(getChildren(mname))
     }
     c.modules.foreach{ m =>
diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala
index 1db1e1ed..cd55a9a4 100644
--- a/src/main/scala/firrtl/transforms/Dedup.scala
+++ b/src/main/scala/firrtl/transforms/Dedup.scala
@@ -235,7 +235,6 @@ object DedupModules {
     val instances = mutable.Set[WDefInstance]()
     InstanceGraph.collectInstances(instances)(module.asInstanceOf[Module].body)
     val instanceModuleMap = instances.map(i => i.name -> i.module).toMap
-    val moduleNames = instances.map(_.module)
 
     def getNewModule(old: String): DefModule = {
       moduleMap(name2name(old))
diff --git a/src/main/scala/firrtl/transforms/Flatten.scala b/src/main/scala/firrtl/transforms/Flatten.scala
index a94f5d5a..658f0987 100644
--- a/src/main/scala/firrtl/transforms/Flatten.scala
+++ b/src/main/scala/firrtl/transforms/Flatten.scala
@@ -26,7 +26,7 @@ class Flatten extends Transform {
    val inlineTransform = new InlineInstances
    
    private def collectAnns(circuit: Circuit, anns: Iterable[Annotation]): (Set[ModuleName], Set[ComponentName]) =
-     anns.foldLeft(Set.empty[ModuleName], Set.empty[ComponentName]) {
+     anns.foldLeft( (Set.empty[ModuleName], Set.empty[ComponentName]) ) {
        case ((modNames, instNames), ann) => ann match {
          case FlattenAnnotation(CircuitName(c)) =>
            (circuit.modules.collect {
@@ -106,7 +106,6 @@ class Flatten extends Transform {
      annos match {
        case Nil => state
        case myAnnotations =>
-         val c = state.circuit
          val (modNames, instNames) = collectAnns(state.circuit, myAnnotations)
          // take incoming annotation and produce annotations for InlineInstances, i.e. traverse circuit down to find all instances to inline
          val (newc, modsToInline) = duplicateSubCircuitsFromAnno(state.circuit, modNames, instNames)
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 9eee69d4..1f0202d1 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -21,7 +21,6 @@ import scala.collection.mutable
 class RemoveKeywordCollisions(keywords: Set[String]) extends Transform {
   val inputForm: CircuitForm = LowForm
   val outputForm: CircuitForm = LowForm
-  private type Renames = mutable.HashMap[String, String]
   private type ModuleType = mutable.HashMap[String, ir.Type]
   private val inlineDelim = "_"
 
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala
index a1161ac6..945deb7e 100644
--- a/src/main/scala/firrtl/transforms/TopWiring.scala
+++ b/src/main/scala/firrtl/transforms/TopWiring.scala
@@ -70,11 +70,10 @@ class TopWiringTransform extends Transform {
             case d: Port => (true, d.tpe, sourceList(ComponentName(w.name,currentmodule)))
             case _ => throw new Exception(s"Cannot wire this type of declaration! ${w.serialize}")
           }
-          val name = w.name
           sourceMap.get(currentmodule.name) match {
             case Some(xs:Seq[(ComponentName, Type, Boolean, InstPath, String)]) =>
-              sourceMap.update(currentmodule.name, xs :+
-                 (ComponentName(w.name,currentmodule), tpe, isport ,Seq[String](w.name), prefix))
+              sourceMap.update(currentmodule.name, xs :+(
+                 (ComponentName(w.name,currentmodule), tpe, isport ,Seq[String](w.name), prefix) ))
             case None =>
               sourceMap(currentmodule.name) = Seq((ComponentName(w.name,currentmodule),
                                                    tpe, isport ,Seq[String](w.name), prefix))
@@ -103,11 +102,10 @@ class TopWiringTransform extends Transform {
             case d: Port => (true, d.tpe, sourceList(ComponentName(w.name,currentmodule)))
             case _ => throw new Exception(s"Cannot wire this type of declaration! ${w.serialize}")
           }
-          val name = w.name
           sourceMap.get(currentmodule.name) match {
             case Some(xs:Seq[(ComponentName, Type, Boolean, InstPath, String)]) =>
-                sourceMap.update(currentmodule.name, xs :+
-                  (ComponentName(w.name,currentmodule), tpe, isport ,Seq[String](w.name), prefix))
+                sourceMap.update(currentmodule.name, xs :+(
+                  (ComponentName(w.name,currentmodule), tpe, isport ,Seq[String](w.name), prefix) ))
             case None =>
                 sourceMap(currentmodule.name) = Seq((ComponentName(w.name,currentmodule),
                                                      tpe, isport ,Seq[String](w.name), prefix))
diff --git a/src/main/scala/logger/Logger.scala b/src/main/scala/logger/Logger.scala
index 7b9d5acc..acf618e9 100644
--- a/src/main/scala/logger/Logger.scala
+++ b/src/main/scala/logger/Logger.scala
@@ -38,7 +38,7 @@ object LogLevel extends Enumeration {
     case "info"  => LogLevel.Info
     case "debug" => LogLevel.Debug
     case "trace" => LogLevel.Trace
-    case level => throw new Exception("Unknown LogLevel '$level'")
+    case level => throw new Exception(s"Unknown LogLevel '$level'")
   }
 }
 
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