From aa24fe3ece6edcd1c121d6aa6860b6de825bb381 Mon Sep 17 00:00:00 2001
From: Carlos Eduardo
Date: Tue, 9 Mar 2021 20:23:27 -0300
Subject: Fix the readmem statements in nested  block (#2109)

---
 src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
index bc4996df..c7143f5f 100644
--- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
+++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala
@@ -854,11 +854,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
             case MemoryLoadFileType.Binary => "$readmemb"
             case MemoryLoadFileType.Hex    => "$readmemh"
           }
-          val inlineLoad = s"""
-                              |initial begin
-                              |  $readmem("$filename", ${s.name});
-                              |end""".stripMargin
-          memoryInitials += Seq(inlineLoad)
+          memoryInitials += Seq(s"""$readmem("$filename", ${s.name});""")
       }
     }
 
-- 
cgit v1.2.3