From 9cfca577b4effd880f40838f89f2a46f27e88186 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 23 Aug 2018 23:41:01 -0400 Subject: Make InferReadWrite mixin HasScoptOptions Signed-off-by: Schuyler Eldridge --- src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index c83194e8..3494de45 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,6 +8,7 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} +import firrtl.options.HasScoptOptions import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq @@ -15,6 +16,7 @@ import annotations._ import scopt.OptionParser import firrtl.stage.RunFirrtlTransformAnnotation + case object InferReadWriteAnnotation extends NoTargetAnnotation // This pass examine the enable signals of the read & write ports of memories @@ -145,9 +147,18 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased { +class InferReadWrite extends Transform with SeqTransformBased with HasScoptOptions { def inputForm = MidForm def outputForm = MidForm + + def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser + .opt[Unit]("infer-rw") + .abbr("firw") + .valueName ("") + .action( (_, c) => c ++ Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)) ) + .maxOccurs(1) + .text("Enable readwrite port inference for the target circuit") + def transforms = Seq( InferReadWritePass, CheckInitialization, -- cgit v1.2.3