From 8c22ab2ba734b3b83d8a962ffd26e11fab077293 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 24 Mar 2016 14:47:46 -0700
Subject: Fix Chirrtl serialization bug

---
 src/main/scala/firrtl/Serialize.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index 02b9ebc2..7419dbbf 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -137,19 +137,19 @@ private object Serialize {
         s"printf(${serialize(p.clk)}, ${serialize(p.en)}, ${q}${serialize(p.string)}${q}" +
                       (if (p.args.nonEmpty) p.args.map(serialize).mkString(", ", ", ", "") else "") + ")"
       }
-      case s:Empty => "skip"
-      case s:CDefMemory => {
-        if (s.seq) s"smem ${s.name} : ${s.tpe} [${s.size}]"
-        else s"cmem ${s.name} : ${s.tpe} [${s.size}]"
+      case s: Empty => "skip"
+      case s: CDefMemory => {
+        if (s.seq) s"smem ${s.name} : ${serialize(s.tpe)} [${s.size}]"
+        else s"cmem ${s.name} : ${serialize(s.tpe)} [${s.size}]"
       }
-      case s:CDefMPort => {
+      case s: CDefMPort => {
         val dir = s.direction match {
           case MInfer => "infer"
           case MRead => "read"
           case MWrite => "write"
           case MReadWrite => "rdwr"
         }
-        s"${dir} mport ${s.name} = ${s.mem}[${s.exps(0)}], s.exps(1)"
+        s"${dir} mport ${s.name} = ${s.mem}[${serialize(s.exps(0))}], ${serialize(s.exps(1))}"
       }
     }
   }
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