From 87ad4220c2eba50fb1ccc854b20021776c6d34de Mon Sep 17 00:00:00 2001
From: Howard Mao
Date: Thu, 25 Aug 2016 14:56:00 -0700
Subject: Finer grained control over randomization

We previously had `ifdef guards on some parts of the emitted verilog to
control whether some registers or nets should be given random initial
values. These guards were all dependent on the RANDOMIZE macro.

However, there were actually three separate cases being controlled

 1. Giving random values to disconnected wires
 2. Random initialization of registers
 3. Random initialization of memories

It is possible that the designer would want to switch these three on or
off independently in simulation. For instance, the latter two are
usually safe because registers and memories will get some definite
binary value at power on in the actual circuit, but the first one can
be quite dangerous because the undriven wire could be metastable.

This change provides separate macros for each of the three sets of
guards so that they can be controlled independently.
---
 src/main/scala/firrtl/Emitter.scala | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 316a7044..30c764d8 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -316,7 +316,7 @@ class VerilogEmitter extends Emitter {
          assigns += Seq("assign ",e," = ",value,";")
       // In simulation, assign garbage under a predicate
       def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression) = {
-         assigns += Seq("`ifndef RANDOMIZE")
+         assigns += Seq("`ifndef RANDOMIZE_ASSIGN")
          assigns += Seq("assign ", e, " = ", syn, ";")
          assigns += Seq("`else")
          assigns += Seq("assign ", e, " = ", garbageCond, " ? ", rand_string(tpe(syn)), " : ", syn, ";")
@@ -381,14 +381,14 @@ class VerilogEmitter extends Emitter {
          Seq(nx,"[",long_BANG(t) - 1,":0]")
       }
       def initialize(e: Expression) = {
-        initials += Seq("`ifdef RANDOMIZE")
+        initials += Seq("`ifdef RANDOMIZE_REG_INIT")
         initials += Seq(e, " = ", rand_string(tpe(e)), ";")
         initials += Seq("`endif")
       }
       def initialize_mem(s: DefMemory) = {
         val index = WRef("initvar", s.dataType, ExpKind(), UNKNOWNGENDER)
         val rstring = rand_string(s.dataType)
-        initials += Seq("`ifdef RANDOMIZE")
+        initials += Seq("`ifdef RANDOMIZE_MEM_INIT")
         initials += Seq("for (initvar = 0; initvar < ", s.depth, "; initvar = initvar+1)")
         initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, FEMALE), " = ", rstring,";")
         initials += Seq("`endif")
@@ -673,16 +673,30 @@ class VerilogEmitter extends Emitter {
    
          emit(Seq("endmodule"))
       }
-   
+
       build_netlist(m.body)
       build_ports()
       build_streams(m.body)
       emit_streams()
       m
    }
-   
+
+   def emit_preamble() {
+    emit(Seq(
+        "`ifdef RANDOMIZE_ASSIGN\n",
+        "`define RANDOMIZE\n",
+        "`endif\n",
+        "`ifdef RANDOMIZE_REG_INIT\n",
+        "`define RANDOMIZE\n",
+        "`endif\n",
+        "`ifdef RANDOMIZE_MEM_INIT\n",
+        "`define RANDOMIZE\n",
+        "`endif\n"))
+   }
+
    def run(c: Circuit, w: Writer) = {
       this.w = Some(w)
+      emit_preamble()
       for (m <- c.modules) {
          m match {
             case (m:Module) => emit_verilog(m)
-- 
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