From 86f7abd4d63a33bbb0012fa254b01edf10ba2159 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Tue, 1 Aug 2017 16:10:52 -0700
Subject: DCE for IsInvalid (#629)

---
 src/main/scala/firrtl/transforms/DeadCodeElimination.scala | 3 +++
 src/test/scala/firrtlTests/DCETests.scala                  | 2 ++
 2 files changed, 5 insertions(+)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
index aa147733..48978a7a 100644
--- a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -207,6 +207,9 @@ class DeadCodeElimination extends Transform {
         case Attach(info, exprs) => // If any exprs are dead then all are
           val dead = exprs.flatMap(getDeps(_)).forall(deadNodes.contains(_))
           if (dead) EmptyStmt else Attach(info, exprs)
+        case IsInvalid(info, expr) =>
+          val node = getDeps(expr) match { case Seq(elt) => elt }
+          if (deadNodes.contains(node)) EmptyStmt else IsInvalid(info, expr)
         case block: Block => block map onStmt
         case other => other
       }
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index 41edfa8b..ea34d4be 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -109,6 +109,8 @@ class DCETests extends FirrtlFlatSpec {
         |    input x : UInt<1>
         |    input y : UInt<1>
         |    output z : UInt<1>
+        |    x is invalid
+        |    y is invalid
         |    z <= x
         |  module Top :
         |    input x : UInt<1>
-- 
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