From 7cc42d4857855b582b63587fe010051daca85ced Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 16:45:44 -0800
Subject: Added semicolon after assigns in verilog

---
 src/main/stanza/passes.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 000419cc..35165abc 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2392,7 +2392,7 @@ defn emit-verilog (m:InModule) -> Module :
          (t:VectorType) : add(declares,[b " " type(t) " " n " [0:" size(t) - 1 "];"])
          (t) : add(declares,[b " " t " " n ";"])
    defn assign (e:Expression,value:Expression) : 
-      add(assigns,["assign " e " = " value])
+      add(assigns,["assign " e " = " value ";"])
    defn update-and-reset (r:Expression,clk:Expression,reset?:Expression,init:Expression) :
       if not key?(at-clock,clk) : at-clock[clk] = Vector<Streamable>()
 
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