From 6ebd1585e891d0d31cd99ef3e63038b0675cf8f9 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 2 Mar 2018 17:00:10 -0800
Subject: Reduce Statement nesting in Wiring Pass (#751)

Large amounts of Wiring could result in huge nesting of Statements. This could
cause stack overflows using the Mappers. Fixed by no longer nesting Statements
in Wiring Pass.---
 src/main/scala/firrtl/passes/wiring/Wiring.scala | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index a268dba7..8c401753 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -194,8 +194,12 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
           Connect(NoInfo, toExp(l), toExp(r))
         })
         m match {
-          case Module(i, n, ps, s) => Module(i, n, ps ++ ports,
-            Block(defines ++ Seq(s) ++ connects))
+          case Module(i, n, ps, body) =>
+            val stmts = body match {
+              case Block(sx) => sx
+              case s => Seq(s)
+            }
+            Module(i, n, ps ++ ports, Block(defines ++ stmts ++ connects))
           case ExtModule(i, n, ps, dn, p) => ExtModule(i, n, ps ++ ports, dn, p)
         }
     }
-- 
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