From 6eba1d0685f5ee383246eb0c3ec7c06ad413cb34 Mon Sep 17 00:00:00 2001
From: Angie
Date: Fri, 19 Aug 2016 19:38:51 -0700
Subject: Minor utility changes.

* Corrected names to match current RW port spec
* Added Jack's Namespace on Circuit
---
 src/main/scala/firrtl/Namespace.scala       | 9 +++++++++
 src/main/scala/firrtl/passes/MemUtils.scala | 4 ++--
 2 files changed, 11 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index 7d4758c5..93e0ec76 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -84,5 +84,14 @@ object Namespace {
 
     namespace
   }
+
+  /** Initializes a [[Namespace]] for [[Module]] names in a [[Circuit]] */
+  def apply(c: Circuit): Namespace = {
+    val namespace = new Namespace
+    c.modules foreach { m =>
+      namespace.namespace += m.name
+    }
+    namespace
+  }
 }
 
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 4b91d9cd..263422df 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -148,9 +148,9 @@ object MemPortUtils {
   def rwPortToBundle(mem: DefMemory) =
     BundleType(Seq(
       Field("wmode", Default, UIntType(IntWidth(1))),
-      Field("data", Default, mem.dataType),
+      Field("wdata", Default, mem.dataType),
       Field("rdata", Flip, mem.dataType),
-      Field("mask", Default, create_mask(mem.dataType)),
+      Field("wmask", Default, create_mask(mem.dataType)),
       Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))),
       Field("en", Default, UIntType(IntWidth(1))),
       Field("clk", Default, ClockType)))
-- 
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