From 6e7982ba015f5e8b3e1d17086c7abe4eaf04458e Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Mon, 9 Aug 2021 13:29:52 -0700
Subject: PropagatePresetAnnotations: remove false prerequisites (#2323)

The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!---
 src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
index 941dce41..c0251e35 100644
--- a/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
+++ b/src/main/scala/firrtl/transforms/PropagatePresetAnnotations.scala
@@ -40,12 +40,7 @@ object PropagatePresetAnnotations {
   */
 class PropagatePresetAnnotations extends Transform with DependencyAPIMigration {
 
-  override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
-    Seq(
-      Dependency[BlackBoxSourceHelper],
-      Dependency[FixAddingNegativeLiterals],
-      Dependency[ReplaceTruncatingArithmetic]
-    )
+  override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized
 
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