From 6255d5e398ae21dbc75db907bb9a9b24bc09d2b3 Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 19 Aug 2016 16:58:34 -0700
Subject: Added ReplaceSubAccesses before RemoveSubAccesses

---
 src/main/scala/firrtl/LoweringCompilers.scala      |  1 +
 .../scala/firrtl/passes/ReplaceSubAccess.scala     | 32 ++++++++++++++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 src/main/scala/firrtl/passes/ReplaceSubAccess.scala

(limited to 'src')

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index f9a5864c..c8430d2b 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -104,6 +104,7 @@ class ResolveAndCheck () extends Transform with SimpleRun {
 class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun {
    val passSeq = Seq(
       passes.PullMuxes,
+      passes.ReplaceAccesses,
       passes.ExpandConnects,
       passes.RemoveAccesses,
       passes.ExpandWhens,
diff --git a/src/main/scala/firrtl/passes/ReplaceSubAccess.scala b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala
new file mode 100644
index 00000000..8e911a96
--- /dev/null
+++ b/src/main/scala/firrtl/passes/ReplaceSubAccess.scala
@@ -0,0 +1,32 @@
+package firrtl.passes
+
+import firrtl.ir._
+import firrtl.{WRef, WSubAccess, WSubIndex, WSubField}
+import firrtl.Mappers._
+import firrtl.Utils._
+import firrtl.WrappedExpression._
+import firrtl.Namespace
+import scala.collection.mutable
+
+
+/** Replaces constant [[firrtl.WSubAccess]] with [[firrtl.WSubIndex]]
+  * TODO Fold in to High Firrtl Const Prop
+  */
+object ReplaceAccesses extends Pass {
+  def name = "Replace Accesses"
+
+  def run(c: Circuit): Circuit = {
+    def onStmt(s: Statement): Statement = s map onStmt map onExp
+    def onExp(e: Expression): Expression = e match {
+      case WSubAccess(e, UIntLiteral(value, width), t, g) => WSubIndex(e, value.toInt, t, g)
+      case e => e map onExp
+    }
+  
+    val newModules = c.modules map {
+      case m: ExtModule => m
+      case Module(i, n, ps, b) => Module(i, n, ps, onStmt(b))
+    }
+
+    Circuit(c.info, newModules, c.main)
+  }
+}
-- 
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