From 61f3e886affce326a2c09c2f5ba8a69465c0c2ee Mon Sep 17 00:00:00 2001
From: Jiuyang liu
Date: Mon, 26 Oct 2020 15:31:49 +0000
Subject: fix for LoweringCompilersSpec.

---
 src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index ffaaf332..54f0af8e 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -249,6 +249,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers {
       new firrtl.transforms.FlattenRegUpdate,
       firrtl.passes.VerilogModulusCleanup,
       new firrtl.transforms.VerilogRename,
+      firrtl.passes.InferTypes,
       firrtl.passes.VerilogPrep,
       new firrtl.AddDescriptionNodes
     )
@@ -273,6 +274,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers {
       new firrtl.transforms.DeadCodeElimination,
       firrtl.passes.VerilogModulusCleanup,
       new firrtl.transforms.VerilogRename,
+      firrtl.passes.InferTypes,
       firrtl.passes.VerilogPrep,
       new firrtl.AddDescriptionNodes
     )
-- 
cgit v1.2.3