From 5f410f0e4774121932d644f31fde83b9b8ed78be Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 14 Sep 2020 15:02:15 -0400 Subject: Hit connect case in DedupModuleTests (#1716) Signed-off-by: Schuyler Eldridge Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- src/test/scala/firrtlTests/transforms/DedupTests.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index 8c2835dd..8213cb84 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -256,7 +256,7 @@ class DedupModuleTests extends HighTransformSpec { execute(diff_params, diff_params, Seq.empty) } - "Modules with aggregate ports that are bulk connected" should "NOT dedup if their port names differ" in { + "Modules with aggregate ports that are (partial)? connected" should "NOT dedup if their port names differ" in { val input = """ |circuit FooAndBarModule : @@ -271,13 +271,13 @@ class DedupModuleTests extends HighTransformSpec { | inst foo of FooModule | inst bar of BarModule | io.foo <- foo.io - | io.bar <- bar.io + | io.bar <= bar.io |""".stripMargin val check = input execute(input, check, Seq.empty) } - "Modules with aggregate ports that are bulk connected" should "dedup if their port names are the same" in { + "Modules with aggregate ports that are (partial)? connected" should "dedup if their port names are the same" in { val input = """ |circuit FooAndBarModule : @@ -288,10 +288,10 @@ class DedupModuleTests extends HighTransformSpec { | output io : {flip foo : UInt<1>, fuzz : UInt<1>} | io.fuzz <= io.foo | module FooAndBarModule : - | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}} + | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip foo : UInt<1>, fuzz : UInt<1>}} | inst foo of FooModule | inst bar of BarModule - | io.foo <- foo.io + | io.foo <= foo.io | io.bar <- bar.io |""".stripMargin val check = @@ -301,10 +301,10 @@ class DedupModuleTests extends HighTransformSpec { | output io : {flip foo : UInt<1>, fuzz : UInt<1>} | io.fuzz <= io.foo | module FooAndBarModule : - | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}} + | output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip foo : UInt<1>, fuzz : UInt<1>}} | inst foo of FooModule | inst bar of FooModule - | io.foo <- foo.io + | io.foo <= foo.io | io.bar <- bar.io |""".stripMargin execute(input, check, Seq.empty) -- cgit v1.2.3