From 5869b8e201390b534b06b8960ab32351e51602c0 Mon Sep 17 00:00:00 2001 From: ducky Date: Sat, 16 Jan 2016 16:31:16 -0800 Subject: Import a logging library so we don't reinvent the wheel and have implicits flying around everywhere --- src/main/resources/logback.xml | 10 ++++++ src/main/scala/firrtl/DebugUtils.scala | 62 ++-------------------------------- src/main/scala/firrtl/Driver.scala | 55 ++++++++++++++---------------- src/main/scala/firrtl/Passes.scala | 45 ++++++++++++------------ src/main/scala/firrtl/Primops.scala | 10 +++--- 5 files changed, 67 insertions(+), 115 deletions(-) create mode 100644 src/main/resources/logback.xml (limited to 'src') diff --git a/src/main/resources/logback.xml b/src/main/resources/logback.xml new file mode 100644 index 00000000..a6bab96e --- /dev/null +++ b/src/main/resources/logback.xml @@ -0,0 +1,10 @@ + + + + [%-4level] %msg%n + + + + + + diff --git a/src/main/scala/firrtl/DebugUtils.scala b/src/main/scala/firrtl/DebugUtils.scala index e802d935..5d58fba6 100644 --- a/src/main/scala/firrtl/DebugUtils.scala +++ b/src/main/scala/firrtl/DebugUtils.scala @@ -2,7 +2,6 @@ package firrtl -import java.io.PrintWriter import Utils._ private object DebugUtils { @@ -63,67 +62,10 @@ private object DebugUtils { a.ports.foreach(_.preOrderTraversal(f)) a.stmt.preOrderTraversal(f) } - case a: Circuit => a.modules.foreach(_.preOrderTraversal(f)) + case a: Circuit => a.modules.foreach(_.preOrderTraversal(f)) //case _ => throw new Exception(s"Unsupported FIRRTL node ${ast.getClass.getSimpleName}!") - case _ => + case _ => } } } - - - /** Private class for recording and organizing debug information */ - class Logger private ( - writer: PrintWriter, - printMode: Symbol, - printVars: List[Symbol]){ - - // Legal printModes: 'none, 'error, 'warn, 'info, 'debug, 'trace - require(List('none, 'error, 'warn, 'info, 'debug, 'trace) contains printMode) - val errorEnable = List('error, 'warn, 'info, 'debug, 'trace) contains printMode - val warnEnable = List('warn, 'info, 'debug, 'trace) contains printMode - val infoEnable = List('info, 'debug, 'trace) contains printMode - val debugEnable = List('debug, 'trace) contains printMode - val traceEnable = List('trace) contains printMode - val circuitEnable = printVars contains 'circuit - val debugFlags = printVars.map(_ -> true).toMap.withDefaultValue(false) - - def println(message: => String){ - writer.println(message) - } - def error(message: => String){ - if (errorEnable) writer.println(message.split("\n").map("[error] " + _).mkString("\n")) - } - def warn(message: => String){ - if (warnEnable) writer.println(message.split("\n").map("[warn] " + _).mkString("\n")) - } - def info(message: => String){ - if (infoEnable) writer.println(message.split("\n").map("[info] " + _).mkString("\n")) - } - def debug(message: => String){ - if (debugEnable) writer.println(message.split("\n").map("[debug] " + _).mkString("\n")) - } - def trace(message: => String){ - if (traceEnable) writer.println(message.split("\n").map("[trace] " + _).mkString("\n")) - } - def printlnDebug(circuit: Circuit){ - if (circuitEnable) this.println(circuit.serialize(debugFlags)) - } - // Used if not autoflushing - def flush() = writer.flush() - - } - /** Factory object for logger - * - * Logger records and organizes debug information - */ - object Logger - { - def apply(writer: PrintWriter): Logger = - new Logger(writer, 'warn, List()) - def apply(writer: PrintWriter, printMode: Symbol): Logger = - new Logger(writer, printMode, List()) - def apply(writer: PrintWriter, printMode: Symbol, printVars: List[Symbol]): Logger = - new Logger(writer, printMode, printVars) - def apply(): Logger = new Logger(null, 'none, List()) - } } diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index 82eb3962..700ee936 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -1,30 +1,33 @@ package firrtl import java.io._ -import scala.sys.process._ import java.nio.file.{Paths, Files} + import scala.io.Source +import scala.sys.process._ + +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ import Passes._ - trait DriverPass { - def run(input: String, output: String)(implicit logger: Logger) : Unit + def run(input: String, output: String) : Unit } -case class StanzaPass(val passes : Seq[String]) extends DriverPass { - def run(input : String, output : String)(implicit logger : Logger) : Unit = { +case class StanzaPass(val passes : Seq[String]) extends DriverPass with LazyLogging { + def run(input : String, output : String): Unit = { val cmd = Seq("firrtl-stanza", "-i", input, "-o", output, "-b", "firrtl") ++ passes.flatMap(x=>Seq("-x", x)) - println(cmd.mkString(" ")) + logger.info(cmd.mkString(" ")) val ret = cmd.!! - println(ret) + logger.info(ret) } } -case class ScalaPass(val func : Circuit => Circuit) extends DriverPass { - def run(input : String, output : String)(implicit logger : Logger) : Unit = { +case class ScalaPass(val func : Circuit => Circuit) extends DriverPass with LazyLogging { + def run(input : String, output : String): Unit = { var ast = Parser.parse(input, Source.fromFile(input).getLines) val newast = func(ast) - println("Writing to " + output) + logger.info("Writing to " + output) val writer = new PrintWriter(new File(output)) writer.write(newast.serialize()) writer.close() @@ -53,8 +56,7 @@ object DriverPasses { } } -object Driver -{ +object Driver extends LazyLogging { private val usage = """ Usage: java -cp utils/bin/firrtl.jar firrtl.Driver [options] -i -o """ @@ -117,40 +119,34 @@ object Driver )) // Parse input file and print to output - private def firrtl(input: String, output: String)(implicit logger: Logger) + private def firrtl(input: String, output: String) { val ast = Parser.parse(input, Source.fromFile(input).getLines) val writer = new PrintWriter(new File(output)) writer.write(ast.serialize()) writer.close() - logger.printlnDebug(ast) + logger.debug(ast.toString) } - // Should we just remove logger? - private def executePassesWithLogger(ast: Circuit, passes: Seq[Circuit => Circuit])(implicit logger: Logger): Circuit = { + def executePasses(ast: Circuit, passes: Seq[Circuit => Circuit]): Circuit = { if (passes.isEmpty) ast else executePasses(passes.head(ast), passes.tail) } - def executePasses(ast: Circuit, passes: Seq[Circuit => Circuit]): Circuit = { - implicit val logger = Logger() // No logging - executePassesWithLogger(ast, passes) - } - - private def verilog(input: String, output: String)(implicit logger: Logger) { + private def verilog(input: String, output: String) { val outfile = defaultPasses.foldLeft( input ) ( (infile, pass) => { val outfile = genTempFilename(output) pass.run(infile, outfile) outfile }) - println(outfile) + logger.info(outfile) // finally, convert to verilog at the end val cmd = Seq("firrtl-stanza", "-i", outfile, "-o", output, "-X", "verilog") - println(cmd.mkString(" ")) + logger.info(cmd.mkString(" ")) val ret = cmd.!! - println(ret) + logger.info(ret) } def main(args: Array[String]) @@ -220,13 +216,14 @@ object Driver case s: String => nextPrintVar(List(), s.toList) case false => List() } - implicit val logger = options('log) match { + + /*implicit val logger = options('log) match { case s: String => Logger(new PrintWriter(new FileOutputStream(s)), debugMode, printVars) case false => Logger(new PrintWriter(System.err, true), debugMode, printVars) - } + }*/ // -p "printVars" options only print for debugMode > 'debug, warn if -p enabled and debugMode < 'debug - if( !logger.debugEnable && !printVars.isEmpty ) + if (!printVars.isEmpty) logger.warn("-p options will not print unless debugMode (-d) is debug or trace") options('compiler) match { @@ -236,7 +233,7 @@ object Driver } } - def time[R](str: String)(block: => R)(implicit logger: Logger): R = { + def time[R](str: String)(block: => R): R = { val t0 = System.currentTimeMillis() val result = block // call-by-name val t1 = System.currentTimeMillis() diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala index 5aa74630..9469b6cb 100644 --- a/src/main/scala/firrtl/Passes.scala +++ b/src/main/scala/firrtl/Passes.scala @@ -1,11 +1,13 @@ package firrtl +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ import Primops._ -object Passes { +object Passes extends LazyLogging { // TODO Perhaps we should get rid of Logger since this map would be nice ////private val defaultLogger = Logger() @@ -13,7 +15,6 @@ object Passes { // "infer-types" -> inferTypes //) def nameToPass(name: String): Circuit => Circuit = { - implicit val logger = Logger() // throw logging away //mapNameToPass.getOrElse(name, throw new Exception("No Standard FIRRTL Pass of name " + name)) name match { case "infer-types" => inferTypes @@ -22,8 +23,8 @@ object Passes { } } - private def toField(p: Port)(implicit logger: Logger): Field = { - logger.trace(s"toField called on port ${p.serialize}") + private def toField(p: Port): Field = { + logger.debug(s"toField called on port ${p.serialize}") p.dir match { case Input => Field(p.name, Reverse, p.tpe) case Output => Field(p.name, Default, p.tpe) @@ -55,8 +56,8 @@ object Passes { } private def getVectorSubtype(t: Type): Type = t.getType // Added for clarity // TODO Add genders - private def inferExpTypes(typeMap: TypeMap)(exp: Exp)(implicit logger: Logger): Exp = { - logger.trace(s"inferTypes called on ${exp.getClass.getSimpleName}") + private def inferExpTypes(typeMap: TypeMap)(exp: Exp): Exp = { + logger.debug(s"inferTypes called on ${exp.getClass.getSimpleName}") exp.map(inferExpTypes(typeMap)) match { case e: UIntValue => e case e: SIntValue => e @@ -67,8 +68,8 @@ object Passes { case e: Exp => e } } - private def inferTypes(typeMap: TypeMap, stmt: Stmt)(implicit logger: Logger): (Stmt, TypeMap) = { - logger.trace(s"inferTypes called on ${stmt.getClass.getSimpleName} ") + private def inferTypes(typeMap: TypeMap, stmt: Stmt): (Stmt, TypeMap) = { + logger.debug(s"inferTypes called on ${stmt.getClass.getSimpleName} ") stmt.map(inferExpTypes(typeMap)) match { case b: Block => { var tMap = typeMap @@ -95,15 +96,15 @@ object Passes { case s: Stmt => (s, typeMap) } } - private def inferTypes(typeMap: TypeMap, m: Module)(implicit logger: Logger): Module = { - logger.trace(s"inferTypes called on module ${m.name}") + private def inferTypes(typeMap: TypeMap, m: Module): Module = { + logger.debug(s"inferTypes called on module ${m.name}") val pTypeMap = m.ports.map( p => p.name -> p.tpe ).toMap Module(m.info, m.name, m.ports, inferTypes(typeMap ++ pTypeMap, m.stmt)._1) } - def inferTypes(c: Circuit)(implicit logger: Logger): Circuit = { - logger.trace(s"inferTypes called on circuit ${c.name}") + def inferTypes(c: Circuit): Circuit = { + logger.debug(s"inferTypes called on circuit ${c.name}") // initialize typeMap with each module of circuit mapped to their bundled IO (ports converted to fields) val typeMap = c.modules.map(m => m.name -> BundleType(m.ports.map(toField(_)))).toMap @@ -115,8 +116,8 @@ object Passes { def renameall(s : String)(implicit map : Map[String,String]) : String = map getOrElse (s, s) - def renameall(e : Exp)(implicit logger : Logger, map : Map[String,String]) : Exp = { - logger.trace(s"renameall called on expression ${e.toString}") + def renameall(e : Exp)(implicit map : Map[String,String]) : Exp = { + logger.debug(s"renameall called on expression ${e.toString}") e match { case p : Ref => Ref(renameall(p.name), p.tpe) @@ -131,8 +132,8 @@ object Passes { } } - def renameall(s : Stmt)(implicit logger : Logger, map : Map[String,String]) : Stmt = { - logger.trace(s"renameall called on statement ${s.toString}") + def renameall(s : Stmt)(implicit map : Map[String,String]) : Stmt = { + logger.debug(s"renameall called on statement ${s.toString}") s match { case p : DefWire => @@ -165,20 +166,20 @@ object Passes { } } - def renameall(p : Port)(implicit logger : Logger, map : Map[String,String]) : Port = { - logger.trace(s"renameall called on port ${p.name}") + def renameall(p : Port)(implicit map : Map[String,String]) : Port = { + logger.debug(s"renameall called on port ${p.name}") Port(p.info, renameall(p.name), p.dir, p.tpe) } - def renameall(m : Module)(implicit logger : Logger, map : Map[String,String]) : Module = { - logger.trace(s"renameall called on module ${m.name}") + def renameall(m : Module)(implicit map : Map[String,String]) : Module = { + logger.debug(s"renameall called on module ${m.name}") Module(m.info, renameall(m.name), m.ports.map(renameall(_)), renameall(m.stmt)) } - def renameall(map : Map[String,String])(implicit logger : Logger) : Circuit => Circuit = { + def renameall(map : Map[String,String]) : Circuit => Circuit = { c => { implicit val imap = map - logger.trace(s"renameall called on circuit ${c.name} with %{renameto}") + logger.debug(s"renameall called on circuit ${c.name} with %{renameto}") Circuit(c.info, renameall(c.name), c.modules.map(renameall(_))) } } diff --git a/src/main/scala/firrtl/Primops.scala b/src/main/scala/firrtl/Primops.scala index 1840b190..59a6c1ff 100644 --- a/src/main/scala/firrtl/Primops.scala +++ b/src/main/scala/firrtl/Primops.scala @@ -1,10 +1,12 @@ package firrtl +import com.typesafe.scalalogging.LazyLogging + import Utils._ import DebugUtils._ -object Primops { +object Primops extends LazyLogging { private val mapPrimop2String = Map[Primop, String]( Add -> "add", @@ -53,7 +55,7 @@ object Primops { } // Borrowed from Stanza implementation - def lowerAndTypePrimop(e: DoPrimop)(implicit logger: Logger): DoPrimop = { + def lowerAndTypePrimop(e: DoPrimop): DoPrimop = { def uAnd(op1: Exp, op2: Exp): Type = { (op1.getType, op2.getType) match { case (t1: UIntType, t2: UIntType) => UIntType(UnknownWidth) @@ -69,7 +71,7 @@ object Primops { case _ => UnknownType } } - + logger.debug(s"lowerAndTypePrimop on ${e.op.getClass.getSimpleName}") val tpe = e.op match { case Add => uAnd(e.args(0), e.args(1)) @@ -109,7 +111,7 @@ object Primops { case Cat => UIntType(UnknownWidth) case Bit => UIntType(UnknownWidth) case Bits => UIntType(UnknownWidth) - case _ => ??? + case _ => ??? } DoPrimop(e.op, e.args, e.consts, tpe) } -- cgit v1.2.3