From 559cc89a69db6c3b64cac2bdfbf7f78c83ae0e8c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 23 Jan 2016 21:09:25 -0800 Subject: Fix Verilog syntax errors for print/stop --- src/main/stanza/passes.stanza | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index eae4aff2..570e271e 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2452,10 +2452,10 @@ defn emit-verilog (m:InModule) -> Module : add(at-clock[clk],[tab "end"]) add(at-clock[clk],["`endif"]) defn stop (ret:Int) -> Streamable : - ["$fdisplay(32/'h80000002," ret ");$finish;"] + ["$fdisplay(32'h80000002,\"" ret "\");$finish;"] defn printf (str:String,args:List) -> Streamable : val str* = join(List(escape(str),args),",") - ["$fwrite(32/'h80000002," str* ");"] + ["$fwrite(32'h80000002," str* ");"] defn delay (e:Expression, n:Int, clk:Expression) -> Expression : var e* = e for i in 0 to n do : -- cgit v1.2.3