From 519e8c8dea592d2faf949a1a1aa49ea303bd1c72 Mon Sep 17 00:00:00 2001
From: David Biancolin
Date: Wed, 29 Sep 2021 16:58:10 -0700
Subject: TopWiring: filter out unnamed declarations when building source lists
 (#2376)

* Demonstrate a couple failing cases

* Have TopWiring ignore unnamed declarations as potential sources---
 src/main/scala/firrtl/transforms/TopWiring.scala          |  7 +++++--
 src/test/scala/firrtlTests/transforms/TopWiringTest.scala | 11 +++++++++++
 2 files changed, 16 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala
index c231d347..9fc40c59 100644
--- a/src/main/scala/firrtl/transforms/TopWiring.scala
+++ b/src/main/scala/firrtl/transforms/TopWiring.scala
@@ -68,8 +68,11 @@ class TopWiringTransform extends Transform with DependencyAPIMigration {
     state:         CircuitState
   )(s:             Statement
   ): Statement = s match {
-    // If target wire, add name and size to to sourceMap
-    case w: IsDeclaration =>
+    // Declarations with non-empty names can be sources. However, some
+    // side-affecting statements may given the empty string as name. Filter
+    // these out before they are rejected by ComponentName's constructor, since
+    // they cannot be named as a source in a TopWiring annotation anyways.
+    case w: IsDeclaration if w.name != "" =>
       if (sourceList.keys.toSeq.contains(ComponentName(w.name, currentmodule))) {
         val (isport, tpe, prefix) = w match {
           case d: DefWire     => (false, d.tpe, sourceList(ComponentName(w.name, currentmodule)))
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index eb404393..1cee9f74 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -635,6 +635,17 @@ class TopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
     outputState.circuit.serialize should include("output bar_foo")
     outputState.annotations.toSeq should be(empty)
   }
+
+  "Unnamed side-affecting statements" should s"not be included as potential sources" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clock : Clock
+        |    printf(clock, UInt<1>(1), "")
+        |    stop(clock, UInt<1>(1), 1)
+        |""".stripMargin
+    execute(input, input, Seq())
+  }
 }
 
 class AggregateTopWiringTests extends MiddleTransformSpec with TopWiringTestsCommon {
-- 
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