From 4e69f7fe305eb67de0b50713d298869f64d889f3 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 4 Apr 2016 12:02:53 -0700
Subject: Wrapped delay in ifndef verilator, as it is not supported by
 verilator

---
 src/main/scala/firrtl/Emitter.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 82b307ba..5be17cd1 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -554,7 +554,9 @@ class VerilogEmitter extends Emitter {
             emit(Seq("`ifndef SYNTHESIS"))
             emit(Seq("  integer initvar;"))
             emit(Seq("  initial begin"))
-            emit(Seq("    #0.002;"))
+            emit(Seq("    `ifndef verilator"))
+            emit(Seq("      #0.002;"))
+            emit(Seq("    `endif"))
             for (x <- initials) {
                emit(Seq(tab,x))
             }
-- 
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