From 33c0b4312aec944caa62087663ba9ca41c9c9a6e Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Tue, 27 Apr 2021 03:02:58 +0000 Subject: deprecate memlib APIs modifided in #2191. (#2199) --- .../passes/memlib/CreateMemoryAnnotations.scala | 29 ++++++++++++++++++++++ .../scala/firrtl/passes/memlib/DecorateMems.scala | 28 --------------------- .../firrtl/passes/memlib/ReplaceMemMacros.scala | 13 ++++++++++ .../firrtl/passes/memlib/ReplaceMemTransform.scala | 4 +++ src/test/scala/firrtlTests/ReplSeqMemTests.scala | 1 + 5 files changed, 47 insertions(+), 28 deletions(-) create mode 100644 src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala delete mode 100644 src/main/scala/firrtl/passes/memlib/DecorateMems.scala (limited to 'src') diff --git a/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala b/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala new file mode 100644 index 00000000..ce7eea5e --- /dev/null +++ b/src/main/scala/firrtl/passes/memlib/CreateMemoryAnnotations.scala @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: Apache-2.0 + +package firrtl +package passes +package memlib + +import firrtl.stage.Forms + +@deprecated("CreateMemoryAnnotations will not take reader: Option[YamlFileReader] as argument since 1.5.", "FIRRTL 1.4") +class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform with DependencyAPIMigration { + + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def optionalPrerequisiteOf = Forms.MidEmitters + override def invalidates(a: Transform) = false + + def execute(state: CircuitState): CircuitState = reader match { + case None => state + case Some(r) => + import CustomYAMLProtocol._ + val configs = r.parse[Config] + val oldAnnos = state.annotations + val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { + case ((annos, pins), config) => + (annos, pins :+ config.pin.name) + } + state.copy(annotations = PinAnnotation(pins.toSeq) +: as) + } +} diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala deleted file mode 100644 index 1cdecdfa..00000000 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 - -package firrtl -package passes -package memlib - -import firrtl.stage.Forms - -class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform with DependencyAPIMigration { - - override def prerequisites = Forms.MidForm - override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Forms.MidEmitters - override def invalidates(a: Transform) = false - - def execute(state: CircuitState): CircuitState = reader match { - case None => state - case Some(r) => - import CustomYAMLProtocol._ - val configs = r.parse[Config] - val oldAnnos = state.annotations - val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { - case ((annos, pins), config) => - (annos, pins :+ config.pin.name) - } - state.copy(annotations = PinAnnotation(pins.toSeq) +: as) - } -} diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala index 63ae0490..bb2bed33 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala @@ -24,6 +24,7 @@ object ReplaceMemMacros { * This will not generate wmask ports if not needed. * Creates the minimum # of black boxes needed by the design. */ +@deprecated("ReplaceMemMacros will not take writer: ConfWriter as argument since 1.5.", "FIRRTL 1.4") class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm @@ -121,11 +122,14 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM }) ) + @deprecated("memToBundle will become private in 1.5.", "FIRRTL 1.4") def memToBundle(s: DefAnnotatedMemory) = BundleType( s.readers.map(Field(_, Flip, rPortToBundle(s))) ++ s.writers.map(Field(_, Flip, wPortToBundle(s))) ++ s.readwriters.map(Field(_, Flip, rwPortToBundle(s))) ) + + @deprecated("memToFlattenBundle will become private in 1.5.", "FIRRTL 1.4") def memToFlattenBundle(s: DefAnnotatedMemory) = BundleType( s.readers.map(Field(_, Flip, rPortToFlattenBundle(s))) ++ s.writers.map(Field(_, Flip, wPortToFlattenBundle(s))) ++ @@ -136,6 +140,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM * The wrapper module has the same type as the memory it replaces * The external module */ + @deprecated("createMemModule will become private in 1.5.", "FIRRTL 1.4") def createMemModule(m: DefAnnotatedMemory, wrapperName: String): Seq[DefModule] = { assert(m.dataType != UnknownType) val wrapperIoType = memToBundle(m) @@ -162,18 +167,22 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM // TODO(shunshou): get rid of copy pasta // Connects the clk, en, and addr fields from the wrapperPort to the bbPort + @deprecated("defaultConnects will become private in 1.5.", "FIRRTL 1.4") def defaultConnects(wrapperPort: WRef, bbPort: WSubField): Seq[Connect] = Seq("clk", "en", "addr").map(f => connectFields(bbPort, f, wrapperPort, f)) // Generates mask bits (concatenates an aggregate to ground type) // depending on mask granularity (# bits = data width / mask granularity) + @deprecated("maskBits will become private in 1.5.", "FIRRTL 1.4") def maskBits(mask: WSubField, dataType: Type, fillMask: Boolean): Expression = if (fillMask) toBitMask(mask, dataType) else toBits(mask) + @deprecated("adaptReader will become private in 1.5.", "FIRRTL 1.4") def adaptReader(wrapperPort: WRef, bbPort: WSubField): Seq[Statement] = defaultConnects(wrapperPort, bbPort) :+ fromBits(WSubField(wrapperPort, "data"), WSubField(bbPort, "data")) + @deprecated("adaptWriter will become private in 1.5.", "FIRRTL 1.4") def adaptWriter(wrapperPort: WRef, bbPort: WSubField, hasMask: Boolean, fillMask: Boolean): Seq[Statement] = { val wrapperData = WSubField(wrapperPort, "data") val defaultSeq = defaultConnects(wrapperPort, bbPort) :+ @@ -189,6 +198,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM } } + @deprecated("adaptReadWriter will become private in 1.5.", "FIRRTL 1.4") def adaptReadWriter(wrapperPort: WRef, bbPort: WSubField, hasMask: Boolean, fillMask: Boolean): Seq[Statement] = { val wrapperWData = WSubField(wrapperPort, "wdata") val defaultSeq = defaultConnects(wrapperPort, bbPort) ++ Seq( @@ -211,6 +221,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM private type NameMap = collection.mutable.HashMap[(String, String), String] /** Construct NameMap by assigning unique names for each memory blackbox */ + @deprecated("constructNameMap will become private in 1.5.", "FIRRTL 1.4") def constructNameMap(namespace: Namespace, nameMap: NameMap, mname: String)(s: Statement): Statement = { s match { case m: DefAnnotatedMemory => @@ -223,6 +234,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM s.map(constructNameMap(namespace, nameMap, mname)) } + @deprecated("updateMemStmts will be private in 1.5.", "FIRRTL 1.4") def updateMemStmts( namespace: Namespace, nameMap: NameMap, @@ -250,6 +262,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Transform with DependencyAPIM case sx => sx.map(updateMemStmts(namespace, nameMap, mname, memPortMap, memMods)) } + @deprecated("updateMemMods will be private in 1.5.", "FIRRTL 1.4") def updateMemMods(namespace: Namespace, nameMap: NameMap, memMods: Modules)(m: DefModule) = { val memPortMap = new MemPortMap diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index f0325e8e..515ac691 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -43,6 +43,7 @@ object PassConfigUtil { } } +@deprecated("ConfWriter will be removed in 1.5.", "FIRRTL 1.4") class ConfWriter(filename: String) { val outputBuffer = new CharArrayWriter def append(m: DefAnnotatedMemory) = { @@ -111,6 +112,7 @@ class SimpleTransform(p: Pass, form: CircuitForm) extends Transform { class SimpleMidTransform(p: Pass) extends SimpleTransform(p, MidForm) // SimpleRun instead of PassBased because of the arguments to passSeq +@deprecated("Migrate to a SeqTransform. API will be changed in 1.5.", "FIRRTL 1.4") class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigration { override def prerequisites = Forms.MidForm @@ -132,6 +134,7 @@ class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigrat ) ) + @deprecated("API will be replaced with a val in 1.5.", "FIRRTL 1.4") def transforms(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter): Seq[Transform] = Seq( new SimpleMidTransform(Legalize), @@ -144,6 +147,7 @@ class ReplSeqMem extends Transform with HasShellOptions with DependencyAPIMigrat new WiringTransform ) + @deprecated("API will be removed in 1.5.", "FIRRTL 1.4") def execute(state: CircuitState): CircuitState = { val annos = state.annotations.collect { case a: ReplSeqMemAnnotation => a } annos match { diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 2156e392..84709a21 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -30,6 +30,7 @@ class ReplSeqMemSpec extends SimpleTransformSpec { } ) + @deprecated("API will be changed in 1.5.", "FIRRTL 1.4") def checkMemConf(filename: String, mems: Set[MemConf]) { // Read the mem conf val text = FileUtils.getText(filename) -- cgit v1.2.3