From 25a0500dca7e83381739483886c462d7a87721a0 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 18 Apr 2017 11:12:13 -0700 Subject: "Scope" test resource (top.cpp). (#398) Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.--- src/test/resources/firrtl/testTop.cpp | 97 ++++++++++++++++++++++++ src/test/resources/top.cpp | 97 ------------------------ src/test/scala/firrtlTests/FirrtlSpec.scala | 6 +- src/test/scala/firrtlTests/IntegrationSpec.scala | 4 +- src/test/scala/firrtlTests/StringSpec.scala | 2 +- 5 files changed, 104 insertions(+), 102 deletions(-) create mode 100644 src/test/resources/firrtl/testTop.cpp delete mode 100644 src/test/resources/top.cpp (limited to 'src') diff --git a/src/test/resources/firrtl/testTop.cpp b/src/test/resources/firrtl/testTop.cpp new file mode 100644 index 00000000..ba27c917 --- /dev/null +++ b/src/test/resources/firrtl/testTop.cpp @@ -0,0 +1,97 @@ +// See LICENSE for license details. + +#include +#include + +#if VM_TRACE +# include // Trace file format header +#endif + +// Override Verilator definition so first $finish ends simulation +// Note: VL_USER_FINISH needs to be defined when compiling Verilator code +void vl_finish(const char* filename, int linenum, const char* hier) { + Verilated::flushCall(); + exit(0); +} + +using namespace std; + +//VGCDTester *top; +TOP_TYPE *top; + +vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. You can also use a double, if you wish. + +double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does +} + +// TODO Provide command-line options like vcd filename, timeout count, etc. +const long timeout = 100000000L; + +int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); // Remember args + top = new TOP_TYPE; + +#if VM_TRACE // If verilator was invoked with --trace + Verilated::traceEverOn(true); // Verilator must compute traced signals + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + top->trace (tfp, 99); // Trace 99 levels of hierarchy + tfp->open ("dump.vcd"); // Open the dump file +#endif + + + top->reset = 1; + + cout << "Starting simulation!\n"; + + while (!Verilated::gotFinish() && main_time < timeout) { + if (main_time > 15) { + top->reset = 0; // Deassert reset + } + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + + if (main_time >= timeout) { + cout << "Assertion failed! Simulation terminated by timeout at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + return -1; + } else { + cout << "Simulation completed at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + } + + // Run for 10 more clocks + vluint64_t end_time = main_time + 100; + while (main_time < end_time) { + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + +#if VM_TRACE + if (tfp) tfp->close(); +#endif +} + diff --git a/src/test/resources/top.cpp b/src/test/resources/top.cpp deleted file mode 100644 index ba27c917..00000000 --- a/src/test/resources/top.cpp +++ /dev/null @@ -1,97 +0,0 @@ -// See LICENSE for license details. - -#include -#include - -#if VM_TRACE -# include // Trace file format header -#endif - -// Override Verilator definition so first $finish ends simulation -// Note: VL_USER_FINISH needs to be defined when compiling Verilator code -void vl_finish(const char* filename, int linenum, const char* hier) { - Verilated::flushCall(); - exit(0); -} - -using namespace std; - -//VGCDTester *top; -TOP_TYPE *top; - -vluint64_t main_time = 0; // Current simulation time - // This is a 64-bit integer to reduce wrap over issues and - // allow modulus. You can also use a double, if you wish. - -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -// TODO Provide command-line options like vcd filename, timeout count, etc. -const long timeout = 100000000L; - -int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); // Remember args - top = new TOP_TYPE; - -#if VM_TRACE // If verilator was invoked with --trace - Verilated::traceEverOn(true); // Verilator must compute traced signals - VL_PRINTF("Enabling waves...\n"); - VerilatedVcdC* tfp = new VerilatedVcdC; - top->trace (tfp, 99); // Trace 99 levels of hierarchy - tfp->open ("dump.vcd"); // Open the dump file -#endif - - - top->reset = 1; - - cout << "Starting simulation!\n"; - - while (!Verilated::gotFinish() && main_time < timeout) { - if (main_time > 15) { - top->reset = 0; // Deassert reset - } - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - - if (main_time >= timeout) { - cout << "Assertion failed! Simulation terminated by timeout at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - return -1; - } else { - cout << "Simulation completed at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - } - - // Run for 10 more clocks - vluint64_t end_time = main_time + 100; - while (main_time < end_time) { - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - -#if VM_TRACE - if (tfp) tfp->close(); -#endif -} - diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index 6bf73a80..f77b47f3 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -16,7 +16,9 @@ import firrtl.annotations import firrtl.util.BackendCompilationUtilities trait FirrtlRunners extends BackendCompilationUtilities { - lazy val cppHarness = new File(s"/top.cpp") + + val cppHarnessResourceName: String = "/firrtl/testTop.cpp" + /** Compiles input Firrtl to Verilog */ def compileToVerilog(input: String, annotations: AnnotationMap = AnnotationMap(Seq.empty)): String = { val circuit = Parser.parse(input.split("\n").toIterator) @@ -64,7 +66,7 @@ trait FirrtlRunners extends BackendCompilationUtilities { annotations: AnnotationMap = new AnnotationMap(Seq.empty)) = { val testDir = compileFirrtlTest(prefix, srcDir, customTransforms, annotations) val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + copyResourceToFile(cppHarnessResourceName, harness) // Note file copying side effect val verilogFiles = verilogPrefixes map { vprefix => diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index f4173143..6ac45b6d 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -37,8 +37,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec { topFile should exist // Copy harness over - val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + val harness = new File(testDir, s"testTop.cpp") + copyResourceToFile(cppHarnessResourceName, harness) // topFile will be compiled by Verilator command by default but we need to also include dutFile verilogToCpp(top, testDir, Seq(dutFile), harness).! diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index b3f6523d..7e7c040e 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -18,7 +18,7 @@ class PrintfSpec extends FirrtlPropSpec { val prefix = "Printf" val testDir = compileFirrtlTest(prefix, "/features") val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + copyResourceToFile(cppHarnessResourceName, harness) verilogToCpp(prefix, testDir, Seq(), harness).! cppToExe(prefix, testDir).! -- cgit v1.2.3