From 221214070fb357a8cf1a8758a35230242c3a350f Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Sun, 29 Mar 2020 23:10:16 -0700
Subject: Make InlineCasts invalidate LegalizeClocks

---
 src/main/scala/firrtl/transforms/InlineCasts.scala | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/InlineCasts.scala b/src/main/scala/firrtl/transforms/InlineCasts.scala
index 59520228..e6800d60 100644
--- a/src/main/scala/firrtl/transforms/InlineCasts.scala
+++ b/src/main/scala/firrtl/transforms/InlineCasts.scala
@@ -6,7 +6,7 @@ package transforms
 import firrtl.ir._
 import firrtl.Mappers._
 import firrtl.PrimOps.Pad
-import firrtl.options.{Dependency, PreservesAll}
+import firrtl.options.Dependency
 
 import firrtl.Utils.{isCast, isBitExtract, NodeMap}
 
@@ -66,7 +66,7 @@ object InlineCastsTransform {
 }
 
 /** Inline nodes that are simple casts */
-class InlineCastsTransform extends Transform with PreservesAll[Transform] {
+class InlineCastsTransform extends Transform {
   def inputForm = UnknownForm
   def outputForm = UnknownForm
 
@@ -81,6 +81,11 @@ class InlineCastsTransform extends Transform with PreservesAll[Transform] {
 
   override val dependents = Seq.empty
 
+  override def invalidates(a: Transform): Boolean = a match {
+    case _: LegalizeClocksTransform => true
+    case _ => false
+  }
+
   def execute(state: CircuitState): CircuitState = {
     val modulesx = state.circuit.modules.map(InlineCastsTransform.onMod(_))
     state.copy(circuit = state.circuit.copy(modules = modulesx))
-- 
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