From 7992c5f7725bcbf00c1130c50719711b19dc9818 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 15:41:57 -0700 Subject: Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct --- src/main/stanza/passes.stanza | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 0b586080..453a8181 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -712,12 +712,17 @@ defn expand-expr (e:Expression) -> List : for x in generate-entry(name(f),type(f)) map : EF(WSubfield(i,name(x),type(x),gender(e)),flip(x)) else : - val b = exp(e) - val exps = for x in generate-entry(name(b as WRef),type(b)) map : - EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT) - val begin = index-of-elem(type(b) as BundleType,name(e)) + val exps = expand-expr(exp(e)) + val begin = index-of-elem(type(exp(e)) as BundleType,name(e)) val len = num-elems(type(e)) - headn(tailn(exps,begin),len) + val ret = headn(tailn(exps,begin),len) + for r in ret map : EF(exp(r),DEFAULT) + ;val b = exp(e) + ;val exps = for x in generate-entry(name(b as WRef),type(b)) map : + ;EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT) + ;val begin = index-of-elem(type(b) as BundleType,name(e)) + ;val len = num-elems(type(e)) + ;headn(tailn(exps,begin),len) (e:WIndex) : val exps = expand-expr(exp(e)) val len = num-elems(type(e)) @@ -740,6 +745,11 @@ defn size (s:DefMemory) -> Int : size(type(s)) defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType) defn kind (e:WSubfield) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex) defn kind (e:WIndex) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex) +defn base-name (e:Expression) -> Symbol : + match(e) : + (e:WRef) : name(e) + (e:WSubfield) : base-name(exp(e)) + (e:WIndex) : base-name(exp(e)) defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression : match(e) : @@ -749,18 +759,6 @@ defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression : defn lower (body:Stmt) -> Stmt : defn lower-stmt (s:Stmt) -> Stmt : - defn calc-gender (g:Gender, e:Expression) -> Gender : - match(e) : - (e:WRef) : gender(e) - (e:WSubfield) : - println-all-debug(["Calc gender. " g " with " e]) - println-all-debug(["Exp: " exp(e)]) - val flip = bundle-field-flip(name(e),type(exp(e))) - println-all-debug(["Flip: " flip]) - calc-gender(flip * g,exp(e)) - (e:WIndex) : gender(e) - (e) : g - println(s) match(s) : (s:DefWire) : Begin $ @@ -1974,5 +1972,4 @@ public defn run-passes (c: Circuit, p: List,file:String) : if contains(p,'X') or contains(p,'n') : do-stage("Split Expressions", split-exp) if contains(p,'X') or contains(p,'o') : do-stage("Real IR", to-real-ir) if contains(p,'X') or contains(p,'F') : do-stage("To Flo", emit-flo{file,_}) - println("Done!") -- cgit v1.2.3 From 7c0d0af5b91fcdc2a0cf9619b76be5529968487d Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 16:16:33 -0700 Subject: Made temp name generation counter, as well as the name, based off the eventual named assignment. Should be very clear what caused the generation of the temp, and the numbering is based off of that cause, not a global counter --- src/main/stanza/passes.stanza | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 453a8181..39795a62 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -141,6 +141,18 @@ defmethod print (o:OutputStream, g:Gender) : defmethod type (exp:UIntValue) -> Type : UIntType(width(exp)) defmethod type (exp:SIntValue) -> Type : SIntType(width(exp)) +;============== GENSYM STUFF ====================== + +val sym-hash = HashTable(symbol-hash) +defn firrtl-gensym (s:Symbol) -> Symbol : + val cur = get?(sym-hash,s,0) + val nxt = cur + 1 + sym-hash[s] = nxt + symbol-join([s cur]) + +defn firrtl-gensym () -> Symbol : + firrtl-gensym(`gen) + ;============== DEBUG STUFF ============================= public var PRINT-TYPES : True|False = false public var PRINT-KINDS : True|False = false @@ -251,7 +263,7 @@ defmethod map (f: Type -> Type, e: WSubfield) : defmethod map (f: Type -> Type, e: WIndex) : WIndex(exp(e), value(e), f(type(e)), gender(e)) -;================= Temparary Variable Elimination ======================== +;================= Temporary Variable Elimination ======================== ; Returns a new Circuit where temporary variables are removed and returns ; the resulting nested expression @@ -1538,14 +1550,14 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod (e:UIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w)) add(v,WGeq(w*,IntWidth(ceil-log2(value(e))))) UIntValue(value(e),w*) (w) : e (e:SIntValue) : match(width(e)) : (w:UnknownWidth) : - val w* = VarWidth(gensym(`w)) + val w* = VarWidth(firrtl-gensym(`w)) add(v,WGeq(w*,IntWidth(1 + ceil-log2(abs(value(e)))))) SIntValue(value(e),w*) (w) : e @@ -1590,7 +1602,7 @@ defn replace-var-widths (c:Circuit,h:HashTable) -> Circuit : defn remove-unknowns-w (w:Width) -> Width : match(w) : - (w:UnknownWidth) : VarWidth(gensym(`w)) + (w:UnknownWidth) : VarWidth(firrtl-gensym(`w)) (w) : w defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t) @@ -1700,8 +1712,9 @@ defn split-exp (c:Circuit) : match(map(split-exp-e{_,v,n},e)): (e:Subfield|DoPrim|Pad|ReadPort|Register|WritePort) : val n* = - if n typeof False : gensym(`T) - else : to-symbol $ string-join $ [n as Symbol gensym(`#)] + if n typeof False : firrtl-gensym(`T) + else : firrtl-gensym(symbol-join([n as Symbol `#])) + ;to-symbol $ string-join $ [n as Symbol firrtl-gensym(`#)] add(v,DefNode(n*,e)) WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER) (e) : e @@ -1914,7 +1927,7 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : (s:DefNode) : if value(s) typeof WritePort : val e = value(s) as WritePort - val n = gensym(`F) + val n = firrtl-gensym(`F) emit-all([top "::" n " = wr'" prim-width(type(e)) " " enable(e) " " mem(e) " " index(e) " " name(s) "\n"], top) else : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) -- cgit v1.2.3 From 0608bfbe363780132c0baf1e7098013ab4352f34 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 29 Apr 2015 19:23:03 -0700 Subject: Fixed bug where a node's width was not equal to its value's --- src/main/stanza/passes.stanza | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 39795a62..5d2abb81 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -1520,7 +1520,12 @@ defn gen-constraints (m:Module, h:HashTable, v:Vector) -> Mod (s:DefWire) : DefWire(name(s),h[name(s)]) (s:DefInstance) : DefInstance(name(s),gen-constraints(module(s))) (s:DefMemory) : DefMemory(name(s),h[name(s)] as VectorType) - (s:DefNode) : DefNode(name(s),gen-constraints(value(s))) + (s:DefNode) : + val l = h[name(s)] + val r = gen-constraints(value(s)) + add(v,WGeq(width!(l),width!(type(r)))) + add(v,WGeq(width!(type(r)),width!(l))) + DefNode(name(s),r) (s:Connect) : val l = gen-constraints(loc(s)) val e = gen-constraints(exp(s)) -- cgit v1.2.3